TPS53667 - 6-Phase D-CAP+ Buck Controller w/ PMBus | Texas Instruments
N.º da peça: TPS53667 ✓ Ativo| Qtd. | Preço unitário | Total |
|---|---|---|
| 1 | $4.22 | $4,22 |
| 10 | $4.05 | $40,50 |
| 100 | $3.71 | $371,00 |
| 500 | $3.38 | $1.690,00 |
| 1.000 | $3.05 | $3.050,00 |
TPS53667 Visão geral
A buck controller (also known as a step-down controller) belongs to the broader hierarchy of voltage regulator -> DC-DC converter -> power management IC -> semiconductor. Multi-phase buck controllers like the TPS53667 extend single-phase buck topologies by interleaving multiple switching phases to reduce input/output ripple, improve transient response, and distribute thermal dissipation - enabling >100 A core rails from a single controller IC. The TPS53667 is targeted at server, datacenter, and ASIC POL applications where multi-rail digital loads demand precise, programmable, and telemetry-enabled supply voltages.
Key features include D-CAP+ modulation for ceramic output capacitor compatibility, PMBus v1.2 system interface for telemetry (VOUT, IOUT, temperature) and programmability (VID, fault thresholds), an internal non-volatile memory (NVM) for storing custom configuration, driverless architecture that drives external NexFET power stages, and on-chip protection including OVP, OCP, and thermal shutdown.
The D-CAP+ hysteretic control scheme offers excellent transient response without a traditional compensation network, which simplifies loop design for high di/dt ASIC loads. The 6-phase interleaved operation, combined with PMBus-driven dynamic voltage scaling, makes this controller well-suited for advanced CPU/ASIC cores requiring fast load-step recovery.
Typical applications include ASIC/CPU core rails in servers and datacenters, high-current point-of-load regulation for FPGA and SoC platforms, telecom and networking line-card processors, and AI accelerator card POL supplies. Multi-phase interleaving is essential where single-phase solutions would incur excessive ripple or losses.
When designing with the TPS53667, pair it with TI's NexFET CSD9549x or CSD96497Q5MC power stages for a fully validated driverless solution. The PMBus address and BOOT voltage are set by external resistor straps, eliminating the need for a separate programming device on the production line.
Alternativas drop-in para TPS53667 — mesmo encapsulamento, compatível pino a pino. Peças de encapsulamento diferente que exigem retrabalho na PCB são excluídas.
Variantes desta série
Modelos da mesma série compatíveis como drop-in com TPS53667 (mesmo formato e footprint) — diferindo em Non-Volatile Memory, Output Voltage Range, Package, Phase Configuration, Topology.
Ferramenta de comparação rápida — selecione peças alternativas para comparação lado a lado:
TPS53667RTAR
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
TPS53681RSBT
✅ Drop-In✓ Em estoque
$3.95 / unidade
Ver ficha técnica →TPS53659
✅ Drop-In📋 Alternativa de referência (fora do catálogo)
TPS53667 Classificações máximas e características elétricas
| Topologia | Multi-phase synchronous buck controller |
| Phase Configuration | 6-phase (interleaved) |
| Control Scheme | D-CAP+ hysteretic |
| Faixa de tensão de saída | 0.5 V to 2.5 V (5 mV steps via 8-bit BOOT) |
| Communication Interface | PMBus v1.2 |
| Non-Volatile Memory | Built-in NVM for custom configuration |
| Compatible Power Stages | TI NexFET (CSD9549x series, CSD96497Q5MC) |
| Driver Type | Driverless (drives external power stages) |
| Protection Features | OVP, OCP, OTP |
| Telemetry | VOUT, IOUT, temperature (via PMBus) |
| Encapsulamento | 40-WQFN 6x6 mm (RTA suffix) |
| Tipo de montagem | Surface Mount |
| Target Applications | ASIC POL, server core rails, high-current POL |
| Status RoHS | Compliant |
| Lead Free | Yes |
Configuração de pinos do TPS53667
| Pino 1 | PVCC — Power supply for internal drivers and analog circuits |
| Pino 2 | V33 — 3.3 V analog supply |
| Pino 3 | BP3V3 — Bypass for 3.3 V internal regulator |
| Pino 4 | V5 — 5 V analog supply |
| Pino 5 | EN — Enable input |
| Pino 6 | VRHOT — VR hot indicator output |
| Pino 7 | PGOOD — Power good output |
| Pino 8 | OVP — Over-voltage protection input |
| Pino 9 | OCP — Over-current protection input |
| Pino 10 | BOOT0 — BOOT voltage bit 0 (LSB) |
| Pino 11 | BOOT1 — BOOT voltage bit 1 |
| Pino 12 | BOOT2 — BOOT voltage bit 2 |
| Pino 13 | BOOT3 — BOOT voltage bit 3 |
| Pino 14 | BOOT4 — BOOT voltage bit 4 |
| Pino 15 | BOOT5 — BOOT voltage bit 5 |
| Pino 16 | BOOT6 — BOOT voltage bit 6 |
| Pino 17 | BOOT7 — BOOT voltage bit 7 (MSB) |
| Pino 18 | SCL — PMBus serial clock |
| Pino 19 | SDA — PMBus serial data |
| Pino 20 | ADDR0 — PMBus address bit 0 |
| Pino 21 | ADDR1 — PMBus address bit 1 |
| Pino 22 | GND — Ground |
| Pino 23 | VSUM — D-CAP+ ripple injection node |
| Pino 24 | FB — Feedback / VOUT sense |
| Pino 25 | COMP — Compensation node |
| Pino 26 | VREF — Internal reference bypass |
| Pino 27 | TSENSE — External temperature sense input |
| Pino 28 | IMON — Current monitor output |
| Pino 29 | PWM1 — Phase 1 PWM output to power stage |
| Pino 30 | PWM2 — Phase 2 PWM output |
| Pino 31 | PWM3 — Phase 3 PWM output |
| Pino 32 | PWM4 — Phase 4 PWM output |
| Pino 33 | PWM5 — Phase 5 PWM output |
| Pino 34 | PWM6 — Phase 6 PWM output |
| Pino 35 | NC — Not connected (per datasheet) |
| Pino 36 | NC — Not connected (per datasheet) |
| Pino 37 | NC — Not connected (per datasheet) |
| Pino 38 | NC — Not connected (per datasheet) |
| Pino 39 | NC — Not connected (per datasheet) |
| Pino 40 | EPAD — Exposed thermal pad - must be soldered to PCB ground for thermal dissipation |
Aplicações típicas
TPS53667 é adequado para 7 aplicaçãos: ASIC Core-Rail Point-of-Load, Server CPU VR13.x / VR14 Core Supply, FPGA / SoC Point-of-Load Regulation, AI Accelerator Card Power, Telecom Line-Card Processor Supply, Datacenter Memory (DDR4/DDR5) Termination, High-Performance Networking ASICs.
ASIC Core-Rail Point-of-Load
The TPS53667's 6-phase interleaved architecture and D-CAP+ control deliver high-current, low-ripple core voltage for ASICs that demand sub-1V rails with high accuracy. With 5 mV BOOT resolution across 0.5 V to 2.5 V and PMBus programmability, the controller provides digital VID control for ASICs that change operating points at runtime. The driverless topology pairs with NexFET smart power stages, keeping controller dissipation low and freeing PCB area around the ASIC.
Recomendado
Server CPU VR13.x / VR14 Core Supply
Server CPUs require multi-phase VR13.x-compliant rails drawing 100 A or more, and the TPS53667 delivers up to 6 interleaved phases for the highest-current cores. PMBus v1.2 telemetry (VOUT, IOUT, temperature) and adaptive voltage positioning optimize power delivery while reporting health back to the BMC. The on-chip NVM stores the OEM-specific configuration, eliminating factory programming steps during server manufacturing.
Recomendado
FPGA / SoC Point-of-Load Regulation
High-performance FPGAs and SoCs often need multiple voltage rails (VCCINT, VCCAUX, VCCO) with strict sequencing and fast transient response. The TPS53667's 6-phase architecture can be configured for a single high-current rail or split into fewer-phase subsystems, and its PMBus interface enables platform-level sequencing alongside other rails. D-CAP+ control provides the fast load-step recovery that FPGA fabric toggling demands without complex compensation.
Recomendado
AI Accelerator Card Power
AI training accelerators (GPU, TPU-class) consume hundreds of amps at sub-1V rails with millisecond transients as compute blocks activate. The TPS53667's 6-phase interleaving distributes the thermal load and reduces ripple below FPGA tolerance, while PMBus reports telemetry to the host system for thermal management. Pairing with NexFET power stages such as the CSD96497Q5MC supports >120 A continuous current at 600 kHz to 1 MHz per phase.
Recomendado
Telecom Line-Card Processor Supply
Telecom line cards integrate network processors that step rapidly between active and idle states, demanding tight load-step regulation. The TPS53667 supports PMBus-driven dynamic voltage scaling so the platform can lower rail voltage during idle to save power. Industrial operating temperature range and the 40-WQFN package's small footprint suit the dense layout of ATCA/AdvancedTCA blades.
Recomendado
Datacenter Memory (DDR4/DDR5) Termination
Although the TPS53667 is optimized for low-voltage high-current cores, its wide 0.5 V to 2.5 V output range covers memory termination rails (VTT) and memory-hub supplies used in datacenter DIMM arrays. Combined with PMBus telemetry and the controller's 6-phase flexibility, the design scales from a single VTT rail to multi-phase configurations feeding dense DIMM clusters. The 40-WQFN (6x6) package and exposed pad support the high-current density characteristic of memory VR topologies.
Recomendado
High-Performance Networking ASICs
Switch and routing ASICs in hyperscale datacenters draw 60-200 A at sub-1V rails with tight transient windows. The TPS53667's D-CAP+ control and per-phase current information combine to provide fast load-step response without the complexity of a Type-III compensator. PMBus telemetry integrates with the switch's management plane, allowing real-time thermal and power monitoring of each ASIC rail across thousands of line cards.
Recomendado
Resumo dos produtos recomendados
Dados de referência de engenharia para TPS53667 — comparação, orientação de projeto e informações de conformidade.
Guia de seleção
Comparação com alternativas
| Parâmetro | Este produto | TPS53667RTAR | TPS53681 | TPS53659 |
|---|---|---|---|---|
| Package | 40-WQFN (6x6 mm) | 40-WQFN (6x6 mm) | 40-WQFN (6x6 mm) | 40-WQFN (6x6 mm) |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Phase Configuration | 6-phase (single output) | 6-phase (single output) | 6+2 / 5+3 (dual output, 8 phases) | 6-phase (single output) |
| Output Voltage Range | 0.5 V to 2.5 V | 0.5 V to 2.5 V | 0.5 V to 2.5 V (per rail) | 0.5 V to 2.5 V |
| Control Scheme | D-CAP+ | D-CAP+ | D-CAP+ | D-CAP+ |
| Configuration Method | External pin straps (BOOT, ADDR, etc.) | External pin straps | External pin straps | More digital content; fewer straps |
| Pin-to-Pin Compatible | Reference design | Yes (p/n suffix only) | No (dual-rail pinout) | No (digital I/O differs) |
| PMBus Version | v1.2 | v1.2 | v1.2 | v1.2 |
| On-chip NVM | Yes | Yes | Yes | Yes |
| Compatible Power Stages | TI NexFET (CSD9549x, CSD96497Q5MC) | TI NexFET (CSD9549x, CSD96497Q5MC) | TI NexFET (CSD9549x) | TI NexFET |
Principais diferenciais
- Driverless architecture reduces controller dissipation (vs TPS53659)
- Dual-rail capability in the same package (vs TPS53681)
- External-pinstrap BOOT setting without factory programming (vs TPS53659)
Notas de projeto
The TPS53667 controller IC itself dissipates only the gate-drive and bias power of the driverless architecture (a few hundred mW). However, the PCB exposed pad MUST be soldered to a continuous ground plane with thermal vias to keep junction temperature in spec. Per TI's WQFN package guidelines, use at least a 6x6 mm copper land with a 4x4 via array (0.3 mm drill, 1 mm pitch) for thermal dissipation in a 6-phase application. Without proper thermal pad soldering, the controller may trigger OTP during high-frequency operation.
For multi-phase buck converters, each phase loop (high-side FET, low-side FET, output inductor) must be routed as a tight, low-inductance loop with the input decoupling capacitor placed as close as possible to the power stage. Per TI's TPS53667EVM-769 reference design guidelines, place the VSUM ripple-injection network on the same layer as the controller, kept away from noisy PWM traces. PWM traces should be length-matched within approximately 2 mm to avoid duty-cycle mismatch between phases. Estimated: at 600 kHz switching frequency with 25 ps/mm propagation, phase-to-phase skew should remain under 5% duty cycle.
Do not insert ferrite beads between the controller and the VOUT sense pin (FB), as the D-CAP+ ripple-injection scheme relies on an unfiltered voltage at the sense point. Also note that the BOOT[7:0] pins and PMBus ADDR[1:0] pins are interpreted at POR only - changes after power-up require either a software REBOOT or a hardware reset to take effect. Finally, do not connect unused NC pins on the package footprint; they should be left floating per the datasheet.
Estimated: with 6 phases running at 600 kHz into 100 A total load from a 12 V input, the system-level efficiency can reach 90% if NexFET smart power stages with 1.2 mOhm Rds(on) are used. The TPS53667 itself contributes <500 mW of dissipation in this scenario (drivers + analog + NVM). PVCC must be supplied from a regulated 5 V rail capable of 100 mA peak inrush during startup - do not back-feed from a slowly rising rail or POR behavior will be unreliable.
PMBus SCL and SDA lines require 2.2 kohm pull-ups to V33 (3.3 V) and must be routed away from PWM traces to avoid capacitive coupling. Per TI's I2C/PMBus layout guidance, keep PMBus traces at least 3 mm from any switching node and keep total bus capacitance below 200 pF to meet PMBus timing margins. The SMBALERT# wire (if used) needs the same 2.2 kohm pull-up and a series resistor of approximately 100 ohm at the controller output for impedance matching.
Informações de conformidade
RoHS-compliant per TI product page. Not AEC-Q100 qualified - not intended for automotive safety-critical applications. Halogen-free status not explicitly stated in verified data.
