АЦП/ЦАП
Товары (2518)
ADC102S051CIMM - 10-Bit 2-Ch 200-500 ksps SAR ADC | TI
The Texas Instruments ADC102S051CIMM is a 10-bit, 2-channel, successive-approximation-register (SAR) analog-to-digital converter with a high-speed serial interface, specified over a sample rate range of 200 ksps to 500 ksps. It is offered in an 8-pin VSSOP (also referenced as MSOP-8 / 8-TSSOP) package and operates from a single +2.7V to +5.25V supply. Per-channel throughput is selected through a dedicated CS/address scheme, and the device draws approximately 1.6 mW at 3V and 200 ksps. An SAR ADC is a type of data converter that uses a binary-search algorithm and a precision DAC inside a feedback loop to digitize an analog input in a fixed number of clock cycles, typically one conversion per N clocks for N bits. SAR ADCs are valued for their deterministic latency, lack of pipeline delay, and excellent DC linearity, making them well suited to multiplexed multi-channel systems, motor control, and instrumentation front ends. Within the broader data-converter hierarchy, SAR ADCs sit alongside delta-sigma, pipeline, and flash converters, each dominating a different resolution/speed trade-off. Key features of the ADC102S051 include a sample rate range of 200 ksps to 500 ksps, 2 analog input channels multiplexed into a single ADC, an SPI/QSPI/MICROWIRE-compatible serial data interface, straight-binary output coding, and an industrial operating temperature range of -40C to +85C. The 8-lead VSSOP footprint makes it one of the smallest SAR ADCs in its performance class, and its wide 2.7V-5.25V supply range allows direct connection to 3.3V or 5V microcontrollers without level shifting. Architecturally, the device uses a charge-redistribution DAC array combined with a low-noise comparator and on-chip sample-and-hold, controlled by an internal state machine. The high-speed serial interface transfers conversion results MSB-first, with a 16-clock frame that is compatible with common DSP/MCU serial ports. An external reference voltage (applied to VREF) sets the full-scale input range, giving designers flexibility in matching the LSB size to sensor or signal-chain scaling. Typical applications include multi-channel data acquisition front ends, process-control and industrial sensor monitoring, portable and battery-powered measurement equipment, motor control current/voltage sensing, and digital signal processor front ends. The wide supply range and low power make it equally suitable for 3.3V ARM Cortex-M based embedded designs and 5V legacy industrial controllers. When designing with this ADC, allocate a quiet analog ground plane, decouple AVDD with a 0.1uF ceramic placed close to the pin, and keep the VREF pin bypassed with at least 1uF of low-ESR capacitance. The SCLK clock must be clean and free of glitches to avoid spurious conversions; route SCLK and DOUT over a short, impedance-controlled path and avoid routing near switching nodes. This page synthesizes distributor pricing, drop-in compatible alternatives, and practical design notes not found on the manufacturer datasheet cover page.
ADC102S051CIMMX - 10-Bit 2-Ch 500ksps SAR ADC | Texas Instruments
Texas Instruments ADC102S051CIMMX is a 2-channel, 10-bit successive-approximation-register (SAR) analog-to-digital converter that samples at rates from 200 ksps up to 500 ksps, housed in an 8-pin MSOP-8 (also referred to as 8-VSSOP) surface-mount package with gull-wing leads. It integrates a true-differential input, a high-speed serial interface (SPI/QSPI/MICROWIRE/DSP-compatible), an internal reference, and an internal oscillator, delivering a complete data-acquisition channel for compact designs. A SAR ADC is a converter architecture that approaches the input voltage one bit at a time using a binary-weighted capacitor DAC and a comparator, then latches the 10-bit result in a single conversion clock. SAR converters inherit a class hierarchy of: SAR ADC -> Nyquist-rate data converter -> analog-to-digital converter -> data-conversion IC -> signal-chain semiconductor. Compared with pipeline or delta-sigma ADCs, SAR parts excel at single-shot latency (no pipeline delay) and deterministic throughput, which makes them preferred for multiplexed control loops and event-triggered sampling where phase and timing are critical. Key electrical specifications include a 2.7V to 5.25V single supply, ±1 LSB INL (max), ±1 LSB DNL (max) with no missing codes, a SINAD of 61.6 dB at 5V supply, and a power dissipation of approximately 1.6 mW at 3V / 200 ksps. The device operates over the -40C to +85C industrial temperature range and exhibits excellent AC performance with THD typically below -76 dB, making it suitable for instrumentation, sensor read-out, and consumer audio processing chains. The internal 2.5V reference and sample-and-hold are factory-trimmed; designers need only an input RC network and a 0.1 uF decoupling capacitor at AVDD. A flexible serial interface operates in modes 0 and 4 (CPOL=0, CPHA=0 / CPOL=0, CPHA=1, with /CS controlled by the master). Two fully-differential input channels are time-multiplexed through the same successive-approximation loop, simplifying front-end filtering. Typical applications include portable industrial telemetry, HVAC sensor digitization, optical-module monitoring, multi-cell battery management system (BMS) data acquisition, consumer audio front-ends, and single-board embedded controllers that already have an MCU or DSP needing analog read-back. The wide supply range lets the part share 3.3V rails with common microcontrollers without level translation. When laying out, place the 1uF AVDD bypass capacitor as close to the AVDD pin as possible and route analog/digital grounds back to a single point to avoid switching noise corrupting the conversion result. When selecting this part over the pin-compatible ADC104S051 (12-bit) or ADC122S051 (12-bit, 200 ksps), verify whether the application needs 10-bit or 12-bit resolution and whether the maximum sample rate of 500 ksps must be preserved.
ADC102S051CIMMX/NOPB - 10-Bit 2-Ch 500ksps SAR ADC | Texas Instruments
The Texas Instruments ADC102S051CIMMX/NOPB is a 10-bit, 2-channel, low-power successive-approximation-register (SAR) analog-to-digital converter with a high-speed SPI/QSPI/MICROWIRE-compatible serial interface, housed in an 8-pin Mini-SOIC (VSSOP/MSOP) package. It supports a fully-specified sample-rate range of 200 ksps to 500 ksps, operates from a single +2.7V to +5.25V supply, and consumes 2.7 mW at 3V or 8.6 mW at 5V typical. An SAR ADC is a successive-approximation analog-to-digital converter that uses a binary-search algorithm against an internal precision DAC to digitize an analog input, one bit per clock cycle. SAR ADCs sit in the broader hierarchy of data converters (ADC -> Nyquist ADC -> SAR ADC -> mixed-signal IC -> semiconductor) and are valued for low latency, deterministic behavior, and excellent DC accuracy, making them the standard choice for multiplexed multi-channel data acquisition systems where small numbers of analog inputs must be digitized with predictable timing. Key features include two single-ended analog input channels with a multiplexer, an external reference input, a true differential input stage, and a straight-binary serial output that is SPI/QSPI/MICROWIRE/DSP-frame compatible. The device guarantees 10-bit no-missing-codes performance over the full sample-rate range, supports an industrial -40C to +85C operating range, and uses an external clock for the conversion process, enabling synchronization in multi-ADC systems. Typical applications include portable instrumentation, multi-channel data loggers, optical-module monitoring, point-of-load system monitoring, and embedded industrial control. Designers favor the ADC102S051 for systems that need more than one analog channel with deterministic latency, plus a serial interface that connects directly to microcontrollers and DSPs without glue logic. When laying out the PCB, place the 0.1uF decoupling capacitor as close as possible to the VDD pin and route the analog inputs as a differential pair (AIN+/AIN-) with a solid ground plane. Hold SCLK low during CS high to prevent spurious conversions and respect the tACQ and tCONV timing budgets in the manufacturer datasheet to retain full-throughput accuracy at 500 ksps. This page synthesizes distributor pricing, drop-in VSSOP-8 alternatives, and practical design guidance that complements the manufacturer datasheet, helping engineers shorten BOM validation and layout review cycles.
ADC102S101CIMM - 10-Bit 2-Ch 1Msps SAR ADC | Texas Instruments
The Texas Instruments ADC102S101CIMM is a 10-bit, 2-channel, 500 ksps-to-1 Msps successive-approximation-register (SAR) analog-to-digital converter housed in an 8-pin Mini-SOIC/MSOP (VSSOP) package. It operates from a single +2.7 V to +5.25 V supply and consumes only 3.9 mW at 3 V and 11.4 mW at 5 V, making it a low-power CMOS ADC with an SPI-/QSPI-/MICROWIRE-compatible serial interface. Per the TI product page, the converter is fully specified across a 500 ksps-to-1 Msps sample-rate span rather than at a single speed, simplifying design-in for variable-rate data-acquisition front ends. An ADC (analog-to-digital converter) is an integrated circuit that converts continuous analog voltages into discrete digital codes; SAR ADCs in particular use a binary-search algorithm against an internal DAC to resolve N bits in N clock cycles, combining low latency, deterministic conversion time, and excellent DC accuracy with no pipeline delay. Within the broader taxonomy, the ADC102S101 belongs to the precision-data-converter hierarchy: SAR ADC -> data converter -> signal-chain IC -> analog/mixed-signal semiconductor, sitting between slower integrating ADCs and higher-speed pipeline ADCs. Key specifications include 10-bit resolution, 2 single-ended analog input channels with an internal multiplexer, 1 Msps maximum sampling rate (fully specified down to 500 ksps), straight-binary serial data output, and an internal track-and-hold circuit. The wide 2.7 V-to-5.25 V supply range allows direct interface to 3.3 V or 5 V microcontrollers without level shifters, and the SPI-/QSPI-/MICROWIRE-compatible serial output drops straight into most modern MCUs and DSPs. The SAR architecture provides deterministic latency, low power consumption, and strong DC linearity, with an internal bandgap reference and oscillator on-chip. The 8-pin VSSOP footprint suits high-density PCB layouts, and the CMOS process enables low standby current for battery-powered or sleep-mode applications. Typical applications include portable instrumentation, industrial process control, sensor signal conditioning, factory-automation modules, and battery-powered data loggers. The wide supply range and low 3.9 mW at 3 V power budget make it especially attractive for handheld measurement devices. Designers should add a 0.1 microfarad bypass capacitor close to the supply pin and ensure the analog input stays within the common-mode range; the SPI clock should not exceed 10 MHz (max) to preserve conversion accuracy at full 1 Msps.
ADC102S101CIMMX - 10-Bit 1Msps 2-Ch SAR ADC | Texas Instruments
The Texas Instruments ADC102S101CIMMX is a 2-channel, 10-bit successive-approximation-register (SAR) analog-to-digital converter with a sample rate range of 500 ksps to 1 Msps, supplied in an 8-pin MSOP (also referenced as 8-VSSOP / MINI-SOIC / TSSOP-equivalent) surface-mount package. Operating from a single +2.7 V to +5.25 V supply, it draws 3.9 mW at 3 V and 11.4 mW at 5 V, making it one of the lowest-power dual-channel SAR ADCs in its speed class. A successive-approximation ADC is a type of data converter that performs a binary search through internal DAC switching to digitize an analog input one bit at a time per clock cycle. SAR ADCs are valued for their deterministic latency, lack of pipeline delay, and excellent DC accuracy, which is why they dominate precision industrial, instrumentation, and sensor-interface applications. Within the data-converter hierarchy, the ADC102S101 belongs to the SAR converter family, which sits under the broader categories of precision ADC -> ADC/DAC -> data-converter IC -> signal-chain semiconductor. Key specifications of the ADC102S101CIMMX include two single-ended analog input channels routed through an internal analog multiplexer, a high-speed SPI/QSPI/MICROWIRE-compatible serial output, ±1 LSB INL (typical) and ±1 LSB DNL (typical) at 10 bits, an analog input range of 0 V to VDD, and an operating temperature range of -40 °C to +85 °C (screening level: industrial). The reference voltage is taken from the supply pin (VDD), simplifying the external BOM to just decoupling capacitors. Power-down current is typically sub-microamp, supporting battery-powered duty-cycled designs. Architecture-wise, the device uses a charge-redistribution switched-capacitor DAC array combined with a precision comparator and SAR logic block. The track-and-hold front-end acquires the input in roughly 1.5 clock cycles, after which the conversion phase runs for 10 SAR clock cycles, yielding one conversion result every 16 SCLK cycles at full throughput. Typical applications for the ADC102S101CIMMX include multi-channel sensor monitoring in factory automation, temperature/pressure transducer digitizers, portable battery-powered instrumentation, simple data-logging front-ends, and general-purpose multi-channel analog monitoring in industrial control boards where low power and small PCB footprint are priorities. When designing with this part, ensure the analog input pins are driven from low-impedance sources and that VDD is heavily decoupled (typically 1 uF + 0.1 uF) close to the supply pin to prevent digital switching noise from corrupting conversion results. The SCLK input should be clean and free of ringing; a series-termination resistor close to the driving MCU pin is recommended for cables longer than a few centimeters. This page synthesizes distributor pricing (DigiKey, Mouser, Octopart), drop-in pin-compatible alternatives verified against TI's cross-reference tool, and practical design notes drawn from the manufacturer's datasheet typical-application section - content not consolidated on any single distributor page.
ADC102S101CIMMX/NOPB - 10-Bit 2-Channel 1Msps SAR ADC | TI
The Texas Instruments ADC102S101CIMMX/NOPB is a 10-bit, 2-channel, successive-approximation-register (SAR) analog-to-digital converter with sampling rates from 500 ksps to 1 Msps, packaged in an 8-pin MiniSOIC/VSSOP. The converter features an internal track-and-hold circuit and an SPI-/QSPI-/MICROWIRE-/DSP-compatible high-speed serial interface, making it suitable for embedded and industrial data-acquisition front ends. Operating from a single 2.7 V to 5.25 V supply, it draws 3.9 mW at 3 V and 11.4 mW at 5 V while delivering straight-binary serial output over the full industrial temperature range of -40 °C to +85 °C. A successive-approximation ADC is a sampled-data converter that uses a binary-search algorithm and an internal capacitive charge-redistribution DAC to digitize an analog input one bit per clock cycle. SAR ADCs deliver deterministic latency, no-pipeline delay, and excellent dynamic performance for multiplexed multi-channel systems, which is why they dominate industrial instrumentation, motor control, and precision-sensor front ends. The ADC102S101 places two single-ended input channels behind an internal 2-to-1 analog mux, allowing a single serial interface to serve two sensors with deterministic per-channel acquisition. Key features include 10-bit resolution, 1 Msps maximum throughput, single 2.7 V to 5.25 V analog supply, low power consumption, an external reference option, and a shutdown mode that reduces current to microampere levels. The high-speed serial interface is compatible with SPI, QSPI, MICROWIRE and many DSP serial ports, allowing direct connection to microcontrollers and DSPs without glue logic. An external reference pin lets designers trade noise and scale for their analog input range, while internal sequencing keep single-shot logic simple. The 8-lead VSSOP (also known as MiniSOIC or MSOP) footprint is one of the smallest 8-pin SAR ADC packages available, and the industrial -40 °C to +85 °C rating supports factory-floor deployment. Designers should ensure the analog and digital grounds are joined at a single point near the converter, and that the input bandwidth and source impedance obey the datasheet's acquisition-time equations to avoid codes-dependent distortion. Typical applications include portable battery-powered instrumentation, industrial process control and PLC analog front ends, automotive sensor signal conditioning (non-safety), optical-sensor modules, and consumer audio/sensor signal acquisition. Decoupling should follow the typical-application section of the datasheet, with a 1 µF plus 0.1 µF combination on the supply pin and short, symmetric analog-trace routing to both input channels.
ADC10464CIWM - 10-Bit 600ns 4-Input ADC with S/H | Texas Instruments
The Texas Instruments ADC10464CIWM is a 10-bit, 600 ns analog-to-digital converter with a 4-channel input multiplexer and an integrated sample-and-hold amplifier, housed in a 28-pin SOIC (Wide, WM) package. It supports a single 5V analog supply, performs four-channel multiplexed conversion at up to 800 ksamples per second, and dissipates a typical maximum of 235 mW. The part uses a patented multistep (subranging flash) conversion architecture that achieves sub-microsecond conversion times while keeping CMOS-class power consumption. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts a real-world continuous analog voltage or current into a discrete digital code proportional to the input magnitude. ADCs sit within the broader data-converter hierarchy (ADC/DAC) under data acquisition and signal-chain functions. Multiplexed ADCs like the ADC10464 reduce system cost and board area by sharing one converter across multiple analog sources, with internal channel-selection logic and a front-end sample/hold that stabilizes dynamic inputs during conversion. Multistep architectures split the conversion into coarse and fine flash stages to balance speed, die size, and power. Key features of the ADC10464CIWM include four analog inputs selected by channel address pins, an integrated track-and-hold, ±0.5 LSB differential nonlinearity (DNL), ±1 LSB integral nonlinearity (INL), a parallel digital output bus, and an external reference input. The device includes a track/hold acquisition time consistent with the 600 ns conversion budget, supports ratiometric operation, and provides TTL/CMOS-compatible logic interfaces. The wide-body SOIC package eases probing and rework on legacy through-hole-style layouts. The multistep conversion architecture employs two internal flash stages that refine a coarse estimate with a fine flash sub-conversion, reducing comparators versus a true flash design while still delivering sub-microsecond settling. This makes the ADC10464CIWM a strong fit when faster-than-successive-approximation (SAR) speed is required but full-flash power dissipation is unacceptable. The integrated track/hold front-end allows accurate acquisition of fast multiplexed signals without an external buffer. Typical applications include multi-channel data-acquisition systems, industrial process control front ends, instrumentation and metering, sonar/signal-conditioning boards, and legacy 5V-only embedded platforms. The four input channels suit sensor arrays (temperature, pressure, strain) where many physical inputs share a single conversion pipeline. When designing with this ADC, choose a low-impedance input buffer per channel to drive the switched-capacitor sample/hold input, place decoupling close to AVDD/DVDD pins, and isolate the digital output bus from sensitive analog traces. Use a clean, low-noise external reference (or ratiometric supply) to preserve INL/DNL performance. This page synthesizes distributor pricing, same-package drop-in alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers shorten the part-selection and verification cycle.
ADC10464CIWMX/NOPB - 10-Bit 4-Ch 600ns ADC w/ MUX | Texas Instruments
The Texas Instruments ADC10464CIWMX/NOPB is a 10-bit, 4-channel CMOS analog-to-digital converter with input multiplexer and sample/hold, providing up to 800 ksps conversion in a 28-pin SOIC wide-body package. It operates from a single +5V analog supply, supports an external or internal reference of 5V nominal, and uses a parallel digital interface for high-throughput data transfer. According to the manufacturer datasheet, the device dissipates a maximum of 235 mW at full conversion rate. What is an SAR ADC with input multiplexer? Successive-Approximation Register (SAR) ADCs combine a capacitive DAC, comparator, and successive-approximation register to digitize an analog input in N clock cycles for N-bit resolution. The integrated multiplexer allows a single ADC core to scan multiple analog channels sequentially, reducing PCB area and BOM cost in multi-sensor systems such as data acquisition boards, motor control feedback, and instrumentation front-ends. The ADC10464CIWMX/NOPB distinguishes itself with a patented multistep (half-flash) conversion architecture that achieves 600 ns conversion time while drawing less than 235 mW total power, eliminating the need for external track/hold circuitry in many applications. Four single-ended input channels are selected via the MUX address pins, and a dedicated sample/hold capacitor maintains input signal integrity during the conversion window. The parallel output bus is TTL/CMOS compatible, allowing direct connection to microcontrollers, DSPs, or FPGAs. Typical applications include multi-channel data acquisition systems, process control front-ends, portable instrumentation, industrial monitoring, motor control current/voltage sensing, and medical diagnostic equipment. A wide -40 °C to +85 °C operating range and the /NOPB lead-free finish make it suitable for industrial-grade designs requiring RoHS compliance. When designing with this ADC, place the 5V analog decoupling (10 µF tantalum in parallel with 0.1 µF ceramic) within 5 mm of the AVDD pin to reject switching noise. Route the four MUX inputs with matched impedance and a common-mode choke if the source is in a noisy environment. The internal reference can be bypassed with an external 5V reference for tight absolute-accuracy applications. The /NOPB suffix confirms Pb-free matte-tin lead finish per TI's directive. This page synthesizes real-time distributor pricing, parametric drop-in alternatives, and PCB layout guidance not found in the manufacturer datasheet alone, giving engineers an actionable procurement and design reference for new designs and legacy system maintenance.
ADC104S021CIMMX - 10-Bit 200kSPS 4-Ch SAR ADC | TI
The Texas Instruments ADC104S021CIMMX is a 10-bit, 4-channel, successive-approximation-register (SAR) analog-to-digital converter with a high-speed serial interface, sampling at up to 200 kSPS per channel. Housed in a 10-pin MSOP/VSSOP (DGS) package and specified over the -40C to +85C industrial range, the part draws 1.94 mW from a 3V supply or 6.9 mW from a 5V supply, making it one of the lowest-power quad-channel SAR ADCs in its class. A SAR ADC is a type of data converter that uses a binary-search algorithm and an internal capacitive DAC to digitize an analog input in N successive approximation steps (one per output bit). SAR ADCs sit in the data-converter hierarchy below pipelined and delta-sigma ADCs, and are preferred for multi-channel multiplexed systems that need deterministic latency, small latency variation between channels, and true simultaneous-track-and-hold behavior across the input mux. Key specifications include 4 single-ended input channels selected by an internal sequencer, a sample-rate range of 50 kSPS to 200 kSPS, and an analog supply range of +2.7V to +5.25V. The serial output data is straight binary and is compatible with SPI, QSPI, MICROWIRE, and most common DSP serial interfaces, requiring only three digital lines (CS, SCLK, DOUT). The architecture combines a 4-to-1 analog input mux, a low-impedance sample-and-hold, the SAR engine, and an internal reference path that operates directly from VA without needing an external reference. Power-down modes reduce dissipation to microamp levels between conversions, which is critical for battery-powered and power-cycled sensor nodes. Typical applications include portable multi-sensor data loggers, industrial process-control front-ends, optical-module monitor inputs (temperature/laser-bias monitoring in QSFP/SFP transceivers), motor-control feedback rails, and consumer handheld instruments. The wide 2.7V-5.25V supply tolerance lets a single ADC directly digitize both 3.3V and 5V sensor outputs without level translation. When designing with this ADC, keep analog and digital grounds joined at a single star point near the AGND pin and decouple VA with a 1 uF ceramic plus a 0.1 uF X7R placed within 5 mm of the supply pin; SCLK must be clean and free of ringing, and CS must not remain low indefinitely. This page synthesizes distributor stock/price data, drop-in alternatives in the same MSOP-10 footprint, and practical design notes not found in the standalone datasheet to help engineers select, source, and lay out the ADC104S021CIMMX in production BOMs.
ADC104S051CIMM - 10-Bit 4-Ch 200-500ksps SAR ADC | Texas Instruments
The Texas Instruments ADC104S051CIMM is a 10-bit, 4-channel, 200 ksps to 500 ksps successive-approximation analog-to-digital converter (SAR ADC) housed in a 10-pin VSSOP (DGS) package, delivering low-power multi-channel conversion for space-constrained embedded designs. A SAR ADC is a type of analog-to-digital converter that uses a binary-search successive-approximation algorithm against an internal DAC to digitize an input voltage in N clock cycles for N bits of resolution. SAR ADCs sit in the broader hierarchy of data converter -> ADC -> successive-approximation ADC -> precision converter, and are preferred over flash ADCs for their low power, small die area, and ability to deliver 8 to 18 bits of resolution at hundreds of kiloseconds per second. Key features include a single analog supply from 2.7 V to 5.25 V, a high-speed SPI/QSPI/MICROWIRE-compatible serial interface, four single-ended analog input channels multiplexed into the SAR core, and typical power consumption of 2.7 mW at 3 V and 8.6 mW at 5 V. The output data is straight binary, framing each conversion with a 16-bit serial word so that the channel ID is embedded in the upper bits and the 10-bit conversion result is right-aligned. The architecture uses a charge-redistribution DAC array with sample-and-hold on each conversion, producing 10-bit linearity and low-latency deterministic behavior ideal for multiplexed sensor scanning. Industrial-grade temperature range is -40 C to +85 C, and the small VSSOP-10 footprint allows placement next to analog sensor headers on two-layer and four-layer boards. Typical applications include industrial process control, portable instrumentation, battery-powered data loggers, optical sensor monitoring, and consumer multichannel data acquisition. The wide 2.7 V to 5.25 V supply range means a single ADC104S051CIMM can be powered from a 3.3 V microcontroller rail, a 5 V analog rail, or directly from a Li-ion battery stack through a small LDO. When designing with this device, place a 0.1 uF decoupling capacitor within 3 mm of the AVDD pin and keep analog input traces short and guarded to minimize crosstalk between the four channels. The 16-bit serial frame and standard SPI mode 0/3 timing let it interface directly to nearly any microcontroller or DSP without glue logic. This page synthesizes distributor pricing, same-family and cross-brand drop-in alternatives, and practical design notes that are not collected in the manufacturer datasheet, giving engineers a single reference for part selection, footprint reuse, and BOM risk reduction.
ADC104S101CIMM - 10-Bit 4-Ch 1Msps SAR ADC VSSOP-10 | TI
The Texas Instruments ADC104S101CIMM is a 4-channel, 10-bit successive-approximation-register (SAR) analog-to-digital converter that operates over a sample rate range of 500 ksps to 1 Msps, packaged in a 10-pin VSSOP (DGS) surface-mount housing. The device features a high-speed serial (SPI/QSPI/MICROWIRE/DSP-compatible) interface, single analog supply operation from 2.7 V to 5.25 V, and typical power consumption of 3.9 mW at 3 V or 11.4 mW at 5 V, with four single-ended analog input channels selected via the serial interface. A successive-approximation-register ADC is a class of Nyquist-rate data converter that uses a binary-search algorithm against an internal precision DAC to resolve each analog sample into a digital code on a per-conversion cycle. SAR ADCs are valued for their deterministic latency, lack of pipeline delay, and excellent DC accuracy, which is why they remain the dominant architecture for multiplexed multi-channel data acquisition in the 10-bit to 16-bit resolution range at sample rates from 100 ksps to a few Msps. Within the broader taxonomy, the ADC104S101 sits at the SAR -> ADC -> data converter -> signal chain -> mixed-signal IC hierarchy. Key features of the ADC104S101 include 4 input channels, true 10-bit resolution with no missing codes, a specified sample-rate range of 500 ksps to 1 Msps (fully characterized across the range rather than at one point), a single 2.7 V to 5.25 V supply, straight-binary serial output compatible with SPI, QSPI, MICROWIRE and many DSP serial ports, and an industrial operating temperature range of -40C to +85C. The wide 2.7 V to 5.25 V supply range allows direct interfacing to 3.3 V and 5 V microcontrollers without level shifters. The internal SAR architecture combined with an input sample-and-hold and on-chip conversion clock gives the ADC104S101 deterministic, single-cycle conversion latency, simplifying time-multiplexed channel scanning and making it well suited for control loops and synchronized multi-channel measurements. The four channels share a single serial data output and chip-select, which keeps the host-side GPIO count low and enables easy expansion to more channels by cascading additional devices on the same SPI bus. Typical applications include multi-channel sensor monitoring (temperature, pressure, strain-gauge bridges), portable and battery-powered instrumentation, factory-automation analog front ends, motor-control feedback rails, and general-purpose data-acquisition boards for industrial and consumer systems. The wide supply range and low power consumption also suit handheld meter designs where 2x or 3x AA-cell stacks or a single Li-ion cell must be accepted directly. When designing with this part, place a 0.1 uF decoupling capacitor as close as possible to the AVDD pin and a larger 1 uF to 10 uF bulk capacitor at the supply entrance. Keep analog input traces short and guarded, and route the serial clock (SCLK) away from analog input lines to minimize digital coupling into the sample-and-hold. The 10-lead VSSOP package has a small thermal pad, so pay attention to PCB land pattern and solder paste stencil to avoid tombstoning during reflow. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that are not found in the manufacturer datasheet alone, providing a single-page engineering reference for selection, sourcing and PCB implementation.
ADC104S101CIMMX - 10-Bit 4-Ch 500ksps-1Msps SAR ADC | TI
The Texas Instruments ADC104S101CIMMX is a low-power, four-channel CMOS 10-bit analog-to-digital converter with a high-speed serial interface, offered in a 10-pin VSSOP (Mini Small Outline Package) and specified over a sample rate range of 500 ksps to 1 Msps. Based on a successive-approximation register (SAR) architecture with an internal track-and-hold, the converter accepts a 0V to 5.25V analog input range, draws only milliwatts of power, and is fully specified across the industrial -40C to +85C temperature range. What is a SAR ADC? A successive-approximation register analog-to-digital converter is a sampling ADC architecture that converts analog inputs to a digital code one bit at a time using a binary-search algorithm against an internal DAC. SAR ADCs sit in the broader taxonomy of analog-to-digital converter -> data converter -> mixed-signal IC -> semiconductor. Compared to delta-sigma (oversampling) ADCs, SAR parts deliver lower latency, deterministic throughput, and excellent AC/DC performance for multiplexed multi-channel systems running at hundreds-of-ksps to a few Msps. Key features include 4 single-ended input channels multiplexed into a single SAR core, a SPI/QSPI/MICROWIRE-compatible serial interface, an external reference input (typically 5V for full-scale 5V input), ±1 LSB INL/DNL (typical), and CMOS-compatible digital I/O operating from a single 2.7V to 5.25V supply. Internal sequencing eliminates the need for an external sample clock, and the wide input voltage compliance lets the part directly digitize 5V signals without external dividers. Typical applications include 4-channel data-acquisition front ends, industrial process control and sensor monitoring, portable instrumentation, battery monitoring and management, system monitoring on industrial PCs and servers, and consumer audio/video signal monitoring. The wide analog input range, small package, and SPI-compatible interface make it especially useful in cost- and space-constrained embedded systems. When designing with this device, place the input RC filter components close to each analog input pin, keep analog and digital grounds separate, and provide a low-noise external reference for full 10-bit accuracy. For sample rates below 500 ksps the part is fully specified; operation above 1 Msps is not guaranteed. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not found in the manufacturer datasheet alone.
ADC104S101CIMMX/NOPB - 4-Ch 10-Bit 500-1MSPS SAR ADC | TI
The Texas Instruments ADC104S101CIMMX/NOPB is a low-power, four-channel CMOS 10-bit analog-to-digital converter with a high-speed SPI/QSPI/MICROWIRE-compatible serial interface, specified across the full 500 ksps to 1 Msps sample-rate range in a 10-pin MSOP (DGS) package on tape-and-reel. It integrates a successive-approximation register (SAR) architecture with an internal track-and-hold, a 4-channel analog input multiplexer, an on-chip reference buffer, and a high-speed serial output, all in one compact surface-mount IC. An SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is a precision data-conversion architecture that performs one bit of conversion per internal clock cycle using a binary-search algorithm against a known reference voltage. SAR ADCs offer deterministic latency, no pipeline delay, excellent DC accuracy, and very low power consumption relative to their throughput. ADC104S101 belongs to the SAR ADC family within the broader data-converter hierarchy: SAR ADC -> ADC -> data converter -> mixed-signal IC -> semiconductor. Key features include 10-bit resolution, four single-ended analog input channels, throughput from 500 ksps to 1 Msps, single 2.7 V to 5.25 V supply operation, ±1 LSB INL/DNL (max), and a serial interface compatible with SPI, QSPI, and MICROWIRE. The device typically consumes only 3.6 mW at 1 Msps with a 3 V supply and automatically powers down between conversions, drawing microamps in standby. An external reference voltage is required and supports ratiometric measurements. In typical applications, the ADC104S101 is used in multi-channel sensor digitizing, system monitoring (temperature, voltage, current loops), industrial control loops, handheld instrumentation, and consumer audio/video signal-level measurement. The wide input range (0 V to VA, single-ended) and small MSOP footprint suit dense, multi-channel PCBs. The four-channel MUX plus single ADC core reduces BOM versus four separate ADC ICs. When designing with the ADC104S101CIMMX/NOPB, drive each analog input through a low-impedance source (op-amp buffer or RC anti-alias filter) to maintain AC performance, place 0.1 uF ceramic bypass close to VA and VREF, and use GND/power planes to limit digital switching noise. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that complement the official datasheet.
ADC1061CIN/NOPB - 10-Bit 556kSPS µP-Compatible ADC | Texas Instruments
The Texas Instruments ADC1061CIN/NOPB is a 10-bit, single-channel, semi-flash analog-to-digital converter with an on-chip track-and-hold amplifier, housed in a 20-pin PDIP (through-hole DIP) package. It delivers a maximum sampling rate of 556 kSPS, accepts a single unipolar or bipolar analog input, and provides a parallel microprocessor-compatible digital output bus. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous analog voltages into discrete digital codes. Within the signal chain hierarchy, the ADC sits between analog front-end conditioning (amplifiers, filters, multiplexers) and the digital controller. The 10-bit resolution provides 1024 discrete codes, yielding 1 LSB of approximately 4.88 mV across a 0-5 V unipolar input range - well suited for industrial process control, instrumentation, and data-acquisition applications where 8-bit dynamic range is insufficient but 12-16 bit precision is not required. Key features of the ADC1061 include a built-in sample-and-hold (track/hold) function that captures fast-moving input signals without an external SHA, a half-flash (two-step) conversion architecture that reduces die area compared with full-flash designs while still delivering sub-microsecond conversion time, ±0.5 LSB linearity (typical), and TTL/CMOS-compatible digital I/O. The part operates from a single +5 V supply and consumes approximately 130 mW (typical). The semi-flash architecture uses two 5-bit flash ADCs and a DAC to perform a coarse/fine conversion in two clock cycles. The internal track-and-hold has a 40 ns acquisition time, enabling accurate digitisation of signals with bandwidths up to several hundred kHz. The on-chip output latch simplifies interface to 8-bit and 16-bit microprocessors. Typical applications include process control and industrial data acquisition, digital oscilloscopes and instrumentation, multiplexed data-logging systems, automotive sensor digitisation, and the digitising front-end of PC-based instrumentation cards that require a simple parallel interface to legacy 8051- or x86-style microcontrollers. When designing with the ADC1061CIN/NOPB, ensure the analog input is buffered with a low-impedance op-amp (settling time under 200 ns) and that the AVCC pin is well decoupled with both a 10 µF bulk and 0.1 µF ceramic capacitor. Through-hole PDIP is preferred for hand-assembled prototypes and harsh industrial environments where mechanical robustness outweighs board density. This page synthesises distributor pricing, drop-in replacement candidates, application notes, and engineering design guidance that are not aggregated in the original manufacturer datasheet, helping engineers evaluate the ADC1061 quickly for new designs and legacy board maintenance.
ADC10662CIWM/NOPB - 10-Bit 1.5 MSPS Dual-Input ADC | TI
The Texas Instruments ADC10662CIWM/NOPB is a 10-bit, 1.5 MSPS analog-to-digital converter with a dual-input analog multiplexer and on-chip sample-and-hold, housed in a 24-pin SOIC (WM) wide-body package. It uses a two-step sub-ranging flash architecture to deliver 10-bit conversions in 360 ns with only 235 mW typical power dissipation, eliminating the high power and input capacitance penalties of true flash converters. What is a sub-ranging flash ADC? A sub-ranging (or two-step) flash ADC performs coarse conversion with a lower-resolution flash, then a fine conversion with a second flash, effectively partitioning the conversion range to reduce comparator count, power, and input loading. The category hierarchy is: sub-ranging flash ADC -> successive-approximation-flash hybrid ADC -> analog-to-digital converter -> data converter -> signal chain IC -> semiconductor. This architecture is widely used in video, imaging, and instrumentation sub-systems where 8-12 bit resolution and 1-50 MSPS rates must coexist with modest power budgets. Key features of the ADC10662CIWM/NOPB include two analog input channels selected by the MUX pin, an internal sample-and-hold that holds the sampled input through conversion, a 0 V to 5 V analog input range referenced to a single +5 V supply, and TTL/CMOS-compatible digital outputs. Its 1.5 MSPS throughput supports real-time sampling for DSP front ends and disk-drive read channels, while its low-power CMOS design keeps dissipation low even at the maximum sampling rate. The device uses a single +5 V analog supply and a separate +5 V digital supply for noise isolation. Built-in reference, clock, and conversion-start logic simplify interface to microcontrollers and DSPs. The on-chip input multiplexer and sample-and-hold make the device well suited for multi-channel data-acquisition systems where PCB area and component count are constrained. Typical applications include digital signal processor front ends for motor control and instrumentation, disk-drive servo/READ channels, mobile telecommunications baseband conversion, and process-control data-acquisition boards. Designers should note that the pin-compatible ADC10664 (12-bit, same 1.5 MSPS) is available when resolution, not speed, must be increased. The wide 24-SOIC footprint simplifies thermal management compared with small-outline alternatives, and provides robust manufacturing yields.
ADC10662CIWMX - 10-Bit 1.5MSPS ADC w/ 2-Input MUX | Texas Instruments
The Texas Instruments ADC10662CIWMX is a 10-bit, 1.5 MSPS analog-to-digital converter (ADC) with a 2-input analog multiplexer and on-chip sample-and-hold, housed in a 24-pin SOIC wide-body (300 mil) package. It uses an innovative patented multi-step conversion technique to achieve 360 ns conversion time, supports a parallel word-access data interface, and operates from a single +5 V analog supply. The industrial temperature grade (-40C to +85C) and CMOS process make it suitable for mixed-signal embedded designs. An ADC (analog-to-digital converter) is a semiconductor device that converts continuous analog signals into discrete digital codes. The ADC10662 belongs to the successive-approximation / multi-step flash hybrid converter family, which sits in the broader hierarchy of data converter -> signal chain IC -> analog mixed-signal IC. Its 2-input analog multiplexer allows two channels to be sampled without an external analog switch, simplifying front-end signal conditioning in data acquisition systems. Key features include 10-bit resolution, 1.5 MSPS sampling rate (1.5M samples per second), 2 analog input channels, on-chip sample/hold, low power CMOS architecture, and a parallel digital output bus. The wide SOIC-24 package (7.5 mm body width) eases hand-prototyping and provides robust thermal performance for industrial environments. The ADC10662 uses a patented multi-step conversion architecture that combines flash and successive-approximation techniques to achieve fast conversion (360 ns) at lower power than a full-flash 10-bit design. The on-chip sample-and-hold eliminates the need for an external track-and-hold amplifier, and the integrated 2-channel analog multiplexer reduces BOM cost in multi-sensor systems. Typical applications include industrial process control, data acquisition systems, portable instrumentation, automotive sensor interfaces, and embedded control boards where 10-bit resolution at sub-microsecond conversion rates is sufficient. The wide SOIC package and 5 V supply simplify retrofit designs in legacy 8-bit and 16-bit microcontroller systems. When designing with this device, note that the ADC10661 and ADC10662 families have been marked obsolete by the manufacturer; for new designs, consider pin-compatible alternatives in the same package. Decouple AVDD and DVDD separately with 0.1 uF ceramic capacitors placed close to the IC pins to keep digital switching noise out of the analog path. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone manufacturer datasheet - including a cross-package compatibility matrix and verified industry-grade substitutes for EOL replacement planning.
ADC10664CIWM - 10-Bit 360ns 4-Ch ADC w/ Mux & S/H | TI
The Texas Instruments ADC10664CIWM is a 10-bit, 360 ns analog-to-digital converter with a 4-channel input multiplexer and on-chip sample-and-hold, housed in a 28-pin SOIC Wide package. It delivers a maximum sample rate of approximately 1.5 MSPS from a single 5 V analog supply and provides four single-ended analog input channels selected through a 2-bit address, with the fifth conversion on chip 3 being internally connected to an extra channel. An ADC (analog-to-digital converter) is a mixed-signal data converter that transforms a continuous analog input voltage into a discrete digital code. The ADC10664 family combines a flash front-end for the most-significant bits with a successive-approximation stage for the LSBs, which is a hybrid architecture that achieves fast conversion (360 ns typical) while keeping die area and power modest. The on-chip sample-and-hold eliminates the need for an external track-and-hold amplifier and allows the converter to digitize full-scale signals with bandwidths up to the Nyquist limit without an external buffer. Key specifications include 10-bit resolution, 360 ns conversion time (about 2.78 MSPS), 4 single-ended input channels, a built-in sample-and-hold, ±1 LSB linearity (typical), and single 5 V operation. The wide SOIC-28 footprint simplifies layout on standard 0.3-inch DIP-compatible pads and provides a 300-mil body that keeps analog/digital ground separation practical. The /NOPB variants guarantee lead-free and RoHS compliance, while the original CIWM suffix parts may predate the lead-free transition. Typical applications include industrial process control, data acquisition front-ends, instrumentation, sonar and vibration analysis, automotive telemetry, and any 4-channel multiplexed measurement where 10-bit accuracy and microsecond-class latency are sufficient. The 4-input mux allows continuous scanning of up to four sensors without an external analog switch array. When designing, place the AGND and DGND pins with a single-point star connection near the ADC, decouple AVDD with a 10 µF tantalum in parallel with a 0.1 µF ceramic placed within 5 mm of the supply pin, and route the four analog inputs symmetrically to minimize channel-to-channel crosstalk. The reference input is internal; for absolute accuracy, drive REF via a low-impedance buffer rather than using a resistive divider from VCC. The ADC10664 is built on a mature bipolar process and is widely available in long-lifecycle industrial temperature grades, making it well suited for designs that must remain in production for a decade or longer. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that go beyond what the manufacturer datasheet alone provides.
ADC10664CIWMX/NOPB - 10-Bit 360ns ADC, 4-Input MUX | Texas Instruments
The Texas Instruments ADC10664CIWMX/NOPB is a 10-bit, 1.5 MSPS analog-to-digital converter with a built-in 4-input analog multiplexer and sample-and-hold amplifier, housed in a 28-pin SOIC (300-mil) package. It uses a patented multistep flash conversion technique (TI states 360 ns typical conversion time in the datasheet family) to deliver a 10-bit conversion in two sub-steps while dissipating a maximum of approximately 235 mW. The device is specified over the -40 °C to +85 °C industrial temperature range and operates from a single +5 V analog supply. What is a successive-approximation / multi-step flash ADC? An ADC (analog-to-digital converter) translates a continuous analog voltage into a discrete digital code; the ADC10664 sits in the precision data-acquisition family that uses two lower-resolution flash conversions combined with a residue DAC to resolve higher bits in fewer full-scale steps. In the broader signal-chain taxonomy, the ADC10664 is an ADC -> data converter -> mixed-signal IC -> semiconductor. The integrated analog multiplexer lets one ADC share up to four single-ended sources, eliminating external analog switches in multi-channel scanning designs. Key features of the ADC10664 include 10 bits of resolution, 4 single-ended analog input channels, a 1.5 MSPS sampling rate, parallel digital output interface, single-ended input type, and a flash-based multi-step architecture. The on-chip sample-and-hold eliminates the need for an external track-and-hold stage. Housed in a wide-body SOIC-28 package, the device is pin-compatible with TI's broader ADC1066x family and supports standard microprocessor parallel bus read cycles. Architecturally, the ADC10664 uses TI's patented multistep conversion technique that performs two lower-resolution flash conversions and combines them via a switched-capacitor DAC, balancing speed against power dissipation. A self-calibrating ground-reference scheme referenced to the analog supply rejects offset drift over temperature. Typical applications include process control instrumentation, multiplexed data-acquisition front ends, digitizing oscilloscope input stages, industrial sensor digitizers, and portable instrumentation. The 4-channel input multiplexer makes it well suited for multi-sensor scanning systems. The single +5 V supply simplifies board-level power design in mixed 5 V / 3.3 V systems. When designing with this part, take care that the analog input does not exceed the supply rails, place a small RC anti-alias filter in front of each MUX channel, and provide a low-impedance reference decoupling network to keep the internal DAC well settled. This page synthesizes datasheet specifications, distributor pricing and availability, drop-in alternatives from the ADC1066x family, and practical PCB / power design notes not aggregated on a single datasheet page.
ADC10732CIWM - 10-Bit+Sign 2-Ch SAR ADC, SOIC-20 | Texas Instruments
The Texas Instruments ADC10732CIWM (originally introduced by National Semiconductor) is a 10-bit plus sign successive-approximation analog-to-digital converter with two analog input channels, integrated sample-and-hold, and an internal reference, housed in a 20-pin SOIC wide-body package. The device accepts a single +5V analog supply, supports a serial I/O interface using the NSC MICROWIRE-compatible protocol, and delivers a sampling rate of 74 ksps (kiloseconds per second) with a 5 microsecond conversion time. The differential non-linearity is guaranteed to be no missing code, making the converter well-suited for industrial process control loops and instrumentation front-ends. A successive-approximation register (SAR) ADC is a precision converter architecture that performs bit-by-bit comparison against the analog input using an internal DAC, sampling the input through a track-and-hold amplifier and producing a digital word after N internal conversion cycles. SAR ADCs are valued for deterministic latency, zero pipeline delay, and excellent DC accuracy, sitting between slower integrating ADCs and faster but pipeline-introduced flash or pipelined converters. The ADC10732 family targets cost-sensitive multi-channel applications where an integrated reference and minimal external component count are critical. Key features of the ADC10732CIWM include 10-bit resolution with an extended sign bit for 11-bit two's-complement output coding, two analog input channels selectable through an on-chip mux, internal sample-and-hold, internal 2.5V reference, low power consumption suitable for battery-powered systems, and a serial MICROWIRE-compatible interface that minimizes pin count on the host microcontroller. The wide-body 20-SOIC package provides a robust mechanical footprint for industrial through-hole-equivalent surface-mount designs and is rated for the industrial temperature range of -40C to +85C. Architecturally, the converter uses a charge-redistribution DAC array, a precision comparator, and a SAR control sequencer clocked from an internal or external clock. The integrated reference and sample-and-hold eliminate external components, while the serial data interface (SDATA, SCLK, CS) directly interfaces with microcontrollers and DSPs without external latches, reducing both BOM cost and PCB area. Typical applications include industrial process control, portable data acquisition modules, sensor signal conditioning, factory automation front-ends, and portable instrumentation. When designing with this device, the user should observe a 1 microsecond acquisition time between conversions, place the decoupling capacitor close to the analog supply pin, and respect the input common-mode voltage range to ensure full-scale accuracy.
ADC10738CIWMX - 10-Bit+Sign SAR ADC, 74kSPS, 8-Input MUX | TI
The Texas Instruments ADC10738CIWMX is a 10-bit plus sign serial I/O successive-approximation-register (SAR) analog-to-digital converter with an integrated 8-channel analog multiplexer, sample-and-hold amplifier, and 2.5V bandgap reference, housed in a 24-pin SOIC wide-body (WM) package. According to the TI datasheet, the device operates from a single +5V supply, draws 37 mW (maximum) during conversion, and supports a maximum sampling rate of 74 kSPS with a maximum conversion time of 5 us. The integrated 2.5V bandgap reference carries a +/-2% maximum tolerance, and an on-chip serial data output simplifies microcontroller or DSP interface hardware. The CIW suffix indicates the commercial -40C to +85C operating range and the M indicates tape-and-reel packaging. A SAR ADC is a type of analog-to-digital converter that uses a binary search algorithm implemented with a capacitive DAC and a comparator to resolve an input voltage one bit per clock cycle. Compared with integrating or sigma-delta ADCs, SAR converters deliver a deterministic latency per conversion and excellent DC accuracy, making them the workhorse choice for multiplexed data-acquisition systems where many channels must be sampled at moderate rates. The ADC10738 family (which includes the ADC10731, ADC10732, and ADC10734 single-channel variants) adds an 8-input analog MUX plus an internal reference, reducing the total external part count for a multi-channel data-acquisition front end. The 8-input analog MUX lets the host microcontroller cycle through up to eight single-ended analog signals (or four differential pairs) without an external analog switch. The integrated sample-and-hold amplifier acquires the selected input in less than 1 us, while the 2.5V bandgap reference can be used to drive external circuitry or be overdriven with an external reference for ratiometric measurements. A power-down mode reduces current consumption to 18 uW, useful for battery-powered portable instruments that spend most of their life in standby. Typical applications include industrial process control loop monitoring, portable handheld multimeters and DMMs, multi-channel sensor data loggers (temperature, pressure, strain-gauge bridges), and factory-automation front ends. The 8-channel MUX makes the part especially attractive for systems that need to monitor several sensors in sequence rather than simultaneously. The serial data interface reduces pin count versus parallel-output ADCs, which is valuable in cost-sensitive or space-constrained designs. When laying out the PCB, place the 0.1 uF supply bypass capacitor as close as possible to the VDD pin and keep analog input traces short and guarded. The internal reference output requires a 1 uF to 10 uF low-ESR bypass capacitor on REF_OUT; do not load this pin with more than a few hundred microamps. To minimize crosstalk, place digital and analog grounds on separate planes joined at a single point near the ADC. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet. Pricing is current as of 2026-10-12, and lifecycle status reflects the latest data from DigiKey and Mouser.
ADC108S022CIMT - 8-Ch 10-Bit 50-200kSPS SAR ADC | Texas Instruments
The Texas Instruments ADC108S022CIMT is a 10-bit, 8-channel successive-approximation register (SAR) analog-to-digital converter with throughput rates of 50 kSPS to 200 kSPS, housed in a 16-pin TSSOP package. It operates from a 2.7 V to 5.25 V supply, supports eight single-ended analog inputs multiplexed to a single ADC, and uses an SPI/QSPI/MICROWIRE-compatible serial interface. What is a SAR ADC? A successive-approximation register analog-to-digital converter is a type of ADC that performs a binary search across the input voltage using an internal DAC and comparator, producing a single digital code per conversion in N clock cycles (where N is the resolution in bits). SAR ADCs occupy a middle position in the converter hierarchy: they are slower than flash ADCs but faster than integrating or sigma-delta ADCs, and they offer deterministic latency with no pipeline delay, which is essential for multiplexed multi-channel sampling. Within the broader taxonomy, the ADC108S022 belongs to the precision data converter family, the signal-chain IC category, and ultimately the analog semiconductor class. Key features include low power consumption (typically 1.5 mW at 3 V and 200 kSPS), a true-differential analog input architecture with an internal track-and-hold, an external voltage reference input, and a hardware-/software-controlled channel selection register. The part is specified for the industrial temperature range (-40 °C to +105 °C) and provides unipolar input ranges from 0 V to VREF. The serial data frame carries the channel tag and 10-bit conversion result, simplifying firmware decoding. The internal architecture combines an 8-to-1 input MUX, a sample-and-hold amplifier, a precision SAR core, and an internal bandgap-derived reference buffer. With conversion rates scalable via the SCLK input, designers can trade throughput for power dissipation across a wide dynamic range without external clock-generation circuitry. Typical applications include multi-channel sensor monitoring in industrial PLCs, portable instrumentation, battery management systems, HVAC environmental sensors, and consumer white-goods control boards. The wide supply range and small footprint also suit it for distributed I/O modules with strict space and thermal budgets. When designing with this ADC, always bypass VA and VD with 10 µF and 0.1 µF ceramic capacitors placed within 5 mm of the supply pins, and use a low-impedance reference such as the TI REF3040 to avoid code-dependent gain error. This page synthesizes distributor pricing, drop-in alternatives, and practical design guidance that complements the manufacturer datasheet.
ADC108S022CIMTX - 10-Bit 8-Ch 200kSPS SAR ADC | Texas Instruments
The Texas Instruments ADC108S022CIMTX is a 10-bit, 8-channel, successive-approximation-register (SAR) analog-to-digital converter supporting throughput rates from 50 kSPS to 200 kSPS, housed in a 16-pin TSSOP package for the -40C to +105C industrial temperature range. It integrates a low-power CMOS core, an internal track-and-hold circuit, an on-chip conversion clock, and a single-ended analog input multiplexer that selects one of eight input channels (IN0-IN7) per conversion cycle, with serialized straight-binary output through a standard SPI-/QSPI-/MICROWIRE-compatible interface. An ADC (analog-to-digital converter) is a data-acquisition IC that translates continuous analog signals into discrete digital codes for processing by an MCU, DSP, or FPGA. SAR ADCs in particular use a binary-search algorithm with an internal DAC and comparator to achieve a deterministic latency of one conversion cycle per sample and excellent DC linearity, making them the dominant choice for multiplexed multi-channel low-to-medium-speed precision sensing. The ADC108S022 sits inside the broader taxonomy: ADC -> data converter -> data acquisition IC -> signal chain -> mixed-signal semiconductor. Key features include 8 single-ended input channels routed through an analog multiplexer, a true 10-bit no-missing-codes output, a wide analog supply range of 2.7V to 5.25V that allows direct connection to 3.3V or 5V microcontrollers, very low power consumption (typically 1.6 mW at 3V and 200 kSPS), and a power-down mode that reduces supply current to a few hundred nanoamps between conversions for battery-friendly duty-cycled operation. The device is specified across the -40C to +105C extended industrial range, satisfying the operating envelope required for factory automation, building control, and automotive-body electronics. The converter is built on a CMOS process with a successive-approximation register, an internal sample-and-hold capacitor, and a high-accuracy comparator. The reference voltage is supplied externally on the REF pin, allowing the user to scale the input range to match sensor output amplitude; the REF input is not high-impedance (typical equivalent load ~100 kohm during conversion) and must be driven from a low-noise source. The serial digital interface uses CS, SCLK, DOUT, and DIN signals; the latter provides daisy-chain capability for stacking multiple ADCs on one bus. Typical applications include multi-channel sensor monitoring (temperature, pressure, strain-gauge, flow), industrial process control, portable/battery-operated instrumentation, motor-control feedback, optical-module monitoring, and consumer-system housekeeping. The 16-TSSOP footprint and 200 kSPS aggregate rate (25 kSPS per channel when all eight are scanned) match the bandwidth needs of low-frequency transducer signal chains. When designing with this device, always de-couple AVDD and DVDD with 1uF + 0.1uF ceramic capacitors placed within 5 mm of the supply pins, keep the analog reference trace short and guarded with a ground pour, and use a clean low-noise reference source - the converter's noise and linearity inherit directly from REF. A typical 4-wire SPI burst of 16 clocks (12 SCLKs per conversion with 4 framing clocks) easily interfaces to any modern MCU. This page synthesizes distributor pricing, drop-in pin-compatible alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers shorten the BOM selection and layout-review cycle.
ADC108S052CIMT - 8-Channel 10-Bit 500kSPS ADC | Texas Instruments
The Texas Instruments ADC108S052CIMT is an 8-channel, 10-bit successive-approximation-register (SAR) analog-to-digital converter that supports throughput rates from 200 kSPS to 500 kSPS. It comes in a 16-pin TSSOP (PW) package, operates from a 2.7V to 5.25V supply, and is specified over the -40C to +105C industrial temperature range. A SAR ADC is a successive-approximation-register analog-to-digital converter that uses a binary search through an internal DAC to resolve each analog sample in N clock cycles, where N is the resolution in bits. SAR ADCs sit within the broader hierarchy of analog-to-digital converters (ADC -> data converter -> signal chain IC -> mixed-signal semiconductor). They are prized for their deterministic latency, lack of pipeline delay, and excellent DC accuracy for multi-channel multiplexing applications. Key features of the ADC108S052 include eight single-ended analog inputs (IN0 through IN7), a serial SPI/QSPI/MICROWIRE-compatible digital interface, true-differential input capability when paired in pairs, and an integrated track-and-hold circuit. The device draws a low supply current of typically 1.6 mA at 3V supply and 200 kSPS, with auto-power-down between conversions to extend battery life in portable designs. The converter architecture combines a charge-redistribution SAR core with an internal reference and sample-and-hold, achieving 10-bit resolution with no missing codes and INL of 1 LSB (max). The wide 2.7V to 5.25V analog supply range allows direct connection to 3.3V or 5V system rails without level shifting, simplifying PCB design in mixed-voltage systems. Typical applications include multi-zone temperature monitoring systems, industrial sensor arrays (strain, pressure, flow), portable instrumentation and data loggers, optical module monitoring, and motor-control feedback sampling. The eight input channels allow one ADC to replace eight single-channel ADCs in cost- and board-space-constrained designs. When designing with this device, ensure the analog input signal does not exceed V_A or go below GND. A 0.1uF bypass capacitor placed within 5 mm of the supply pin is recommended, and the reference decoupling must use a low-ESR ceramic capacitor. Source impedance above 1 kohm may require an input buffer for full specified accuracy. This page synthesizes distributor pricing from DigiKey/Mouser/Octopart, drop-in same-package alternatives from the TI portfolio, and practical design notes not consolidated in the manufacturer datasheet alone.
ADC108S052CIMTX - 10-Bit 8-Ch 200-500kSPS ADC | TI TSSOP-16
The Texas Instruments ADC108S052CIMTX is a 10-bit, 8-channel, low-power CMOS analog-to-digital converter specified for conversion throughput rates of 200 kSPS to 500 kSPS, housed in a 16-pin TSSOP package. It accepts up to eight single-ended analog inputs (IN0-IN7) and outputs serial data through a single SPI/SSI-compatible serial interface. The converter is built on a successive-approximation register (SAR) architecture with an internal track-and-hold circuit, providing accurate digital conversion across the specified throughput range. What is a SAR ADC? A successive-approximation register analog-to-digital converter is a precision data-conversion topology that compares an analog input against an internal binary-weighted DAC bit-by-bit over multiple clock cycles, ultimately producing a digital code. SAR ADCs sit within the broader category of data converters (ADC/DAC), and are valued for high accuracy, low latency, deterministic sampling, and very small footprint compared to delta-sigma or pipeline alternatives. The ADC108S052 specifically targets cost-sensitive multi-channel applications where 10-bit resolution is sufficient. Key features include 8 input channels with analog input multiplexer, single-ended analog inputs (IN0-IN7), 200 kSPS to 500 kSPS throughput, 10-bit resolution, SPI/SSI-compatible serial output, single 2.7V to 5.25V supply operation, and an industrial operating temperature range of -40C to +105C. The device also includes a hardware/CS pin, SCLK clock input, DOUT data output, and an external conversion-start (CONV) trigger. The SAR architecture delivers zero-latency conversion and inherent anti-alias robustness when paired with an external RC filter. Power consumption scales linearly with throughput, allowing the system designer to trade speed for power by reducing SCLK frequency in battery-powered or low-duty-cycle applications. Typical applications include multi-channel sensor monitoring, industrial process control, portable instrumentation, embedded data acquisition modules, automotive body and HVAC sensor interfaces, and consumer audio level metering. The wide supply range and small TSSOP package make it suitable for high-density multi-signal designs. When designing with this ADC, ensure the analog input bandwidth-limiting RC filter is sized appropriately to reject out-of-band noise below the Nyquist frequency. Decouple AVDD and DVDD separately with 0.1 uF ceramic capacitors placed as close to the IC pins as possible to maintain low digital noise coupling into the analog domain. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone, optimized for engineers evaluating multi-channel ADC options.