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PN5321A3HN-C104-S - 13.56MHz NFC Controller HVQFN-40 | NXP
The NXP PN5321A3HN-C104-S is a highly integrated 13.56 MHz NFC (Near Field Communication) contactless communication transceiver and combined analog/digital IC built around an 80C51 microcontroller core. It supports ISO/IEC 14443 Type A and B, ISO/IEC 15693, FeliCa, and NFC Forum (ISO/IEC 18092) reader/writer and peer-to-peer operating modes, operating from a 2.7 V to 5.5 V supply in a 40-pin HVQFN exposed-pad package. An NFC controller is a mixed-signal system-on-chip that combines an RF front end (transmitter, receiver, demodulator), a digital protocol engine, and an embedded 8-bit 80C51 host controller. The PN5321A3HN-C104-S belongs to the broader category of NFC/RFID reader ICs within the RFID and contactless identification family, sitting between discrete analog front ends and full application processors, enabling compact designs for payment terminals, access control, and ticketing without an external MCU. Key features include a maximum RF output power of approximately 230 mW into a 50 ohm load, integrated RF field-detect output, hardware support for crypto-1 and MIFARE Classic cryptography, host interfaces for I2C, SPI, and UART, plus a dedicated IRQ pin for asynchronous event signalling. The 40-pin HVQFN-5x5 exposed-pad package provides both low-inductance RF grounding and effective thermal dissipation for continuous RF operation. The internal 80C51 core runs at up to 27.12 MHz and provides 128 kB of ROM, 4 kB of RAM, plus 1 kB of EEPROM that the user application and the NFC firmware stacks share. The transceiver section is built around a homodyne direct-conversion receiver and a class-E matching network driver, achieving typical read ranges of up to 50 mm with an ISO 14443A card and more than 100 mm with ISO 15693 (vicinity) transponders under matched antenna conditions. Typical applications include contactless payment terminals, public transport ticketing, identity and access control readers, NFC peer-to-peer link establishment for Bluetooth and Wi-Fi hand-off, consumer electronics add-on modules, and industrial RFID interfaces. Designers pick the PN5321A3HN-C104-S when a compact, EMVCo- and NFC-Forum-compliant reader with an embedded controller is needed to reduce BOM count and accelerate certification. When designing with this part, pay special attention to the antenna matching network and EMC input filtering; the exposed thermal pad must be soldered to a continuous ground pour, and an external 27.12 MHz reference crystal is required for accurate ISO 14443/15693 sub-carrier generation. Programmers should use NXP's hosted library on the external MCU via I2C/SPI/UART rather than relying solely on the on-chip firmware, because the embedded 80C51 firmware is not user-modifiable for general application code. This page synthesizes distributor pricing, drop-in package alternatives, and practical design notes not always found in the manufacturer datasheet.
PN5331B3HN - 13.56MHz NFC Controller, USB Interface | NXP
The NXP Semiconductors PN5331B3HN is a highly integrated Near Field Communication (NFC) transceiver module operating at 13.56 MHz, housed in a 40-pin VFQFN exposed-pad package and built around an 80C51 microcontroller core. The device operates from a 2.5 V to 3.6 V supply, integrates a USB 2.0 full-speed interface, and supports six contactless operating modes spanning ISO/IEC 14443A/MIFARE, ISO/IEC 14443B, FeliCa reader/writer, and card emulation for MIFARE 1 KB/4 KB and FeliCa tags. An NFC controller is a contactless transceiver IC that combines an analog RF front-end (antenna driver, demodulator, load modulator) with a digital protocol stack and host interface. NFC controllers sit between the antenna and the host MCU or SoC, converting 13.56 MHz RF energy into protocol-correct frames for ISO/IEC 14443, ISO/IEC 15693, FeliCa, and peer-to-peer applications. They belong to the broader family of RFID reader/writer ICs, which in turn fall under short-range wireless transceivers and secure connectivity devices used in payments, access control, and identification. The PN5331B3HN's key differentiating features include a maximum RF output power of approximately 200 mW into a 50 ohm load, on-chip transmit/receive frame handling, hard-wired crypto accelerators (MIFARE Classic Crypto1 plus optional secure-element companion over NFC-WI/S2C), and an integrated LOADMOD pin for driving an external active load modulation circuit. The exposed thermal pad of the VFQFN-40 package provides a low theta_JA path, supporting continuous read/write duty cycles typical of payment terminals and access readers. Architecturally, the device integrates an 80C51-compatible core with on-chip ROM/RAM, a dedicated 13.56 MHz air-interface state machine, and a USB 2.0 full-speed PHY. Firmware handles framing, anti-collision, and the upper layers of ISO/IEC 14443-3, while the host driver stack (available from NXP) runs on the external MCU or directly on a Windows/Linux USB host. This split-firmware model has made the PN533 a long-running reference platform for open-source NFC development and for proprietary payment-terminal designs. Typical applications include plug-and-play USB NFC readers for point-of-sale terminals, contactless access-control readers, public-transport validators, and NFC peer-to-peer links for device pairing. The wide protocol coverage also supports industrial asset-tracking readers and embedded NFC modules for handheld POS hardware. A practical design consideration is that the PN5331B3HN must be paired with a properly tuned 50 ohm-matched antenna and EMC-compliant external components per the NXP reference design; deviations in matching network Q can significantly reduce read range. For secure payment applications, an external secure element connected via NFC-WI/S2C is required to store credentials. This page consolidates distributor pricing, drop-in alternatives, and PCB-level design notes derived from the NXP datasheet and reference manuals, providing synthesis not found on any single distributor page.
PN7150B0HN/C11002Y - High-Performance NFC Controller | NXP | VFQFN-40
The NXP PN7150B0HN/C11002Y is a high-performance, full NFC Forum-compliant controller IC operating at 13.56 MHz with integrated firmware and an NCI 1.0 host interface, housed in a 40-pin VFQFN exposed-pad package. It supports FeliCa, ISO 14443 A/B, ISO 15693, MIFARE, and NFC Forum Tag Types 1/2/3/4/5, with a supply voltage range of 2.3 V to 5.5 V and I2C/UART host connectivity. An NFC controller (Near Field Communication controller) is a short-range wireless IC operating at 13.56 MHz that powers contactless identification, pairing, and payment transactions. NFC controllers belong to the broader category of RFID reader/writer ICs within the wireless connectivity IC family, bridging a host processor (via I2C or UART) to an inductive antenna and to in-field tags or peer devices. The PN7150B0HN/C11002Y targets plug-and-play integration, exposing NCI commands so the host runs the NFC Forum stack without low-level driver porting. Key features include integrated firmware (no host-side stack port required), support for all NFC Forum modes (Reader/Writer, Peer-to-Peer, Card Emulation), a configurable host interface (I2C up to 3.4 Mb/s, UART), Dynamic Power Control (DPC) for automatic RF output adjustment, and a wide 2.3 V to 5.5 V supply range that simplifies integration with 3.3 V and 5 V hosts. The part also integrates an LDO, an AHB bridge, and contact-front-end EMC filtering. The PN7150B0HN/C11002Y uses a Cortex-M0 microcontroller core to handle protocol processing on the silicon, offloading the host CPU. The integrated firmware exposes NCI 1.0 commands, allowing the same host stack (Linux, Android, Win IoT) to be reused across product variants. The RF front-end includes an LDO and matched drivers capable of driving typical antennas used in NFC Forum compliance tests. Typical applications include mobile-payment terminals, smart-home hubs, access-control readers, IoT pairing stations, and NFC-enabled printers or POS peripherals. The part is also well suited to industrial HMI panels that need secure, standards-based wireless user authentication. When designing with this IC, dedicate a clean 13.56 MHz antenna layout, observe the matching-component placement guidelines from NXP's hardware design guide, and route the host I2C/UART away from the antenna to avoid coupling. Provide a stable VCC and respect the exposed-pad PCB layout for thermal dissipation. This page synthesizes distributor pricing, drop-in same-brand alternatives, cross-brand competitive parts found in web data, and practical design guidance not aggregated elsewhere.
PN7160A1EV-C100Y - NFC Plug & Play Controller, NCI, VFBGA-64 | NXP
The NXP Semiconductors PN7160A1EV-C100Y is a near-field communication (NFC) plug-and-play controller with an NCI 2.0 host interface and integrated firmware, packaged in a 64-ball VFBGA (C100 suffix) measuring approximately 5 mm x 5 mm x 0.8 mm. It operates the RF front-end at 13.56 MHz, supports FeliCa, ISO/IEC 14443 Type A/B, ISO/IEC 15693, MIFARE and the NFC Forum NCI specification, and is qualified for 1.65 V to 1.95 V digital I/O and 3.0 V to 3.6 V RF supply rails. An NFC controller is the analog/digital interface that powers the contactless radio in a host device. The PN7160A1EV integrates the RF front-end, the protocol stack, and a low-power NCI host interface so the application processor can drive tags, readers, peer-to-peer and card-emulation modes through a standardized I2C command set instead of a proprietary driver. It belongs to the broader taxonomy of NFC/RFID reader ICs -> contactless front-ends -> secure connectivity ICs, and complements NXP's PN71xx family by adding integrated, signed firmware. Key features include on-board load modulation drivers for card-emulation mode, automatic antenna tuning via the integrated VDD_TX and VDD_PA regulators, dynamic power control for battery-powered designs, a low-power standby mode with wake-up via the NCI interface, and integrated firmware that supports all NFC Forum tags and peer modes out of the box. The part also exposes GPIO and IRQ lines for host integration, and includes an integrated temperature sensor for thermal protection. The PN7160A1EV uses an ARM Cortex-M0 core for firmware execution, with hardware accelerators for crypto and framing. The integrated firmware is signed and field-upgradable through NCI, allowing OEMs to support new NFC Forum specifications and proprietary tag types without changing silicon. Designers benefit from the standardized NCI command set, which removes the need for a closed driver on the host processor. Typical applications include NFC payment terminals, mobile point-of-sale (mPOS) readers, secure pairing for Bluetooth/Wi-Fi accessories, ePassport and eID reader kiosks, smart-home commissioning via NFC, and automotive in-cabin wireless charging authentication. The plug-and-play firmware makes it especially attractive for OEMs that lack deep NFC protocol expertise. When designing with the PN7160A1EV-C100Y, observe the VFBGA-64 PCB layout guidelines for the 0.5 mm ball pitch: matched-impedance differential routing between the IC and the antenna matching network, a clean RF ground, and bulk capacitors close to VDD_TX and VDD_PA are essential for radiated performance and EMC compliance. This page synthesizes distributor pricing, drop-in same-package variants, application context and PCB design notes not collated on any single manufacturer page.
PN7160A1HN - NFC Plug & Play Controller, NCI 2.0 | NXP
The NXP PN7160A1HN is an NFC Plug and Play Controller with integrated firmware and NCI 2.0 host interface, housed in a 40-pin HVQFN (6 x 6 mm) package with exposed thermal pad. Operating from 1.65 V to 1.95 V (digital) and 3.0 V to 3.6 V (RF/analog), it supports 13.56 MHz contactless communication and is compliant with ISO 14443, ISO 15693, FeliCa, and NFC Forum standards. The device integrates a new-generation RF contactless front end, an ARM Cortex-M0 microcontroller core with pre-loaded NFC firmware, and an I2C (or SPI) NCI 2.0 host interface, eliminating the need for proprietary device drivers. What is an NFC controller? An NFC (Near Field Communication) controller is a contactless interface IC that drives an external antenna to communicate with tags, smartcards, and peer devices at 13.56 MHz. Compared to a bare RFID frontend, an NFC controller stacks an integrated ARM core + NCI firmware on top of the RF transceiver, exposing only a standardized host interface. NFC controllers sit within the broader hierarchy: NFC controller -> contact/contactless combo IC -> secure element -> NFC Forum-certified modules. NXP's PN7160 family specifically adds Plug & Play behavior so the host reads device descriptors and capability lists automatically, accelerating Linux/Android integration. Key features of the PN7160A1HN include I2C address 0x28 (hardware-fixed), support for card emulation, peer-to-peer, and reader/writer modes, automatic RF field detection with low-power polling down to a few microamps, and broadcast of NDEF message Type 2/3/4/5 tags. The integrated ARM Cortex-M0 executes NXP's NCI 2.0 firmware directly from internal ROM, removing external flash requirements and shortening design-in time. The I2C bus can be reconfigured to SPI through EEPROM settings. Technically, the PN7160A1HN combines an RF analog front end (with sub-1% carrier amplitude stability for card-emulation stability), a digital protocol engine that handles framing, CRC, and anti-collision per ISO 14443-3, and an embedded Cortex-M0 running the NCI stack. Differential TX outputs and two RX inputs drive a passive matched network; an external balun is not needed. Internal LDO blocks keep the analog, RF, and digital rails isolated for maximum PSRR on the RF driver supply. Typical applications include payment terminals, EMVCo contactless readers, NFC tablets and laptops, USB NFC dongles, smart home hubs with tap-to-pair, industrial tag readers, and access control panels. The wide 3.0 V to 5.5 V tolerant RF supply range and high output power help drive antennas through enclosures and PCBs. Designers should place the matching network within 5 mm of the TX1/TX2/RX1/RX2 pins and keep the 27.12 MHz crystal within 2 mm of XTAL1/XTAL2 with a guarded ground ring. The I2C SDA/SCL lines need 4.7 kohm pull-ups to VCC_IO; the IRQ pin should be wired to a host GPIO that can wake the system. Decoupling capacitors must be placed tightly across VBAT, VBAT_PA, and VDDIO pins. This page synthesizes current distributor pricing, same-package drop-in alternatives (PN7161B1HN variants, PN7150 families with different firmware), and practical PCB layout guidance not consolidated in the manufacturer datasheet, helping engineers compare the PN7160A1HN against its siblings and third-party equivalents in a single view.
PN7160A1HN-C100E - NFC Plug & Play Controller, 13.56MHz, HVQFN-40
The NXP Semiconductors PN7160A1HN-C100E is a Near Field Communication (NFC) plug-and-play controller with integrated firmware and NCI (NFC Controller Interface) interface, operating at 13.56 MHz and supporting FeliCa, ISO 14443, ISO 15693, and MIFARE contactless protocols. It comes in a 40-pin HVQFN (6x6 mm) exposed pad package and operates from dual voltage rails: 1.65 V to 1.95 V for the host interface section and 3 V to 3.6 V for the main analog/digital section. An integrated DC-DC converter can be supplied directly from a 2.8 V to 5.5 V battery, simplifying power tree design in portable devices. An NFC controller is a dedicated mixed-signal IC that handles the analog RF front end (transmitter, receiver, AFE, antenna matching) plus the digital protocol stack required to communicate with contactless cards, tags, peer devices, and NFC readers. It sits between the host application processor (which speaks I²C, SPI, or NCI) and the external NFC antenna. Compared to host-side software implementations, an external NFC controller offloads timing-critical protocol handling, improves RF performance, and reduces host CPU load. The PN7160 belongs to the NFC controller (RFID reader IC) product family, with hypernyms: contactless transceiver -> RFID reader -> NFC front-end -> wireless connectivity IC. Key features include full ISO/IEC 14443 Type A/B, ISO/IEC 15693, FeliCa, and MIFARE Classic/Plus/Ultralight/DESFire support, integrated firmware for plug-and-play operation via the standardized NCI 1.0 host interface, automatic antenna tuning (AAT), low-power card detection (LPCD) modes, and support for Reader/Writer, Peer-to-Peer, and Card Emulation modes. The C100 firmware variant is the standard production firmware configuration as released by NXP. The integrated DC-DC and LDO architecture eliminates many external passives and supports direct battery connection between 2.8 V and 5.5 V. Architecturally, the PN7160 combines a high-efficiency RF output stage, an ARM Cortex-M0 core for protocol stack execution, on-chip non-volatile memory for the NCI firmware image, and integrated capacitive sensing for low-power card polling. The device implements the NCI 1.0 specification as defined by the NFC Forum, allowing it to be paired with any NCI-compliant host stack on Linux, Android, Windows, or RTOS-based platforms without modification. This abstraction layer means the same PN7160 silicon can be dropped into designs running NXP, ST, Linux, or third-party NFC middleware. Typical applications include NFC payment terminals (POS), mobile and wearable point-of-sale accessories, Bluetooth pairing and Wi-Fi handover via NFC tap, electronic door locks and access control readers, transit ticketing terminals, and consumer electronics pairing. The low-power card detection mode suits battery-powered access readers and IoT devices that must wake only on tag approach. Design consideration: antenna matching is critical for read range and regulatory compliance. Use NXP's PN7160 hardware design guide (AN12988) reference matching network. Provide adequate copper thermal relief under the exposed pad and ensure the I²C/SPI host lines include pull-ups per the bus specification. This page synthesizes DigiKey/Mouser distributor pricing, datasheet extracts, drop-in same-family alternatives, and practical design notes not assembled in any single manufacturer document.
PN7160A1HN/C100Y - NFC Plug & Play Controller 13.56MHz | NXP
The NXP PN7160A1HN/C100Y is a 13.56 MHz Near Field Communication (NFC) plug-and-play controller with an integrated NCI 2.0 host interface and on-chip firmware, packaged in a 40-pin VFQFN exposed-pad (HVQFN-40, 6x6 mm) form factor. It supports ISO/IEC 14443-A/B, ISO/IEC 15693, FeliCa, MIFARE Classic, MIFARE DESFire, MIFARE Ultralight, and NXP's proprietary NFC-DEP protocols at the air interface, and operates from a 1.65-1.95 V host-side (VDD) supply plus a 3.0-3.6 V NFC front-end (VBAT/VIN) supply over an I2C bus up to 1 MHz. The on-chip firmware handles RF collision resolution, NFC-A/B/F polling loops, and Type 1-5 tag emulation without host CPU involvement, enabling a true drop-in NFC front-end for Linux, Android, Windows, and RTOS systems. What is an NFC controller? An NFC controller is a contactless front-end IC that manages the 13.56 MHz RF link between a device and a contactless card, phone, or tag, offloading the RF protocol stack, AFE/DCI conditioning, and frame-level error handling from the application processor. Within the broader taxonomy, an NFC controller is a subcategory of RFID reader/transponder ICs, itself a subcategory of wireless connectivity ICs within RF & Wireless semiconductors. NXP's PN71xx family targets high-volume consumer and industrial integration where BOM simplification, certified RF performance, and host-CPU offload are critical. The PN7160A1HN/C100Y integrates a high-efficiency RF front-end capable of delivering up to 1 W of TX power to an externally tuned antenna while supporting autonomous low-power card detection. Integrated DC-DC converter and LDO blocks minimize external component count; the part needs only a single 3.3 V supply and a tuned 13.56 MHz antenna loop with EMC filter components. Host connectivity is over I2C with a standardized NCI 2.0 command set, so firmware upgrades and protocol additions are delivered as controller firmware updates rather than host driver rewrites. Typical applications include NFC payment terminals, EMVCo-compliant point-of-sale readers, access control readers, Bluetooth-pairing tap interfaces, IoT provisioning gateways, and industrial identification/logging systems. The PN7161 variant adds Apple Enhanced Contactless Polling (ECP) authorization; the PN7160A1HN/C100Y firmware (C100) does not include ECP and is therefore the default choice for non-Apple-certified designs. Design tip: route the I2C and IRQ lines away from the antenna loop and keep the antenna matching network within 5 mm of the TVSS pin. Provide a solid ground plane beneath the exposed pad (EP) and stitch it with 4-8 thermal vias for thermal relief - the PN7160 dissipates up to 500 mW during continuous RF transmission. This page synthesizes distributor pricing, drop-in pin-compatible alternatives (PN7161 family and PN553/C100 variants), and practical design notes not found in the manufacturer datasheet alone.
PN7160B1EV-C100Y - NFC Plug & Play Controller, 64-VFBGA | NXP
The NXP PN7160B1EV-C100Y is an NFC Plug and Play Controller with Integrated Firmware and NCI Interface, housed in a 64-ball VFBGA package. It operates at 13.56 MHz and supports all major contactless standards including FeliCa, ISO 14443, ISO 15693, MIFARE, and NFC Forum modes. The host interface is SPI, with supply voltages of 1.65V to 1.95V and 3V to 3.6V. An NFC controller is an integrated circuit that implements the physical and protocol layers of Near Field Communication, allowing a host processor to read and write NFC/RFID tags, emulate contactless smart cards, and peer-to-peer data exchange with phones or other NFC devices. The PN7160 belongs to the broader hierarchy: NFC controller -> contactless frontend -> RF IC -> wireless transceiver -> semiconductor. Its integrated firmware and NCI (NFC Controller Interface) compliance remove the need for developers to write low-level stack code, placing the part in the Plug-and-Play category rather than the raw PN512/PN53x register-level controllers. Key differentiating features include support for all NFC Forum modes (Reader/Writer, Peer-to-Peer, Card Emulation), integrated firmware with NCI interface, driver availability for Android, Linux, and Windows, RTOS and bare-metal support, a low-power standby mode with host wake-up via IRQ, and a single 3.3V rail plus a 1.8V host interface supply. The integrated LDO and power management reduce external BOM, while the embedded firmware accelerates time-to-market. Technically, the PN7160 uses a Cortex-M0 microcontroller core running NXP's licensed contactless stack, with on-chip matching network control and automatic antenna tuning support. The RF output stage is compliant with ISO/IEC 14443 type A/B, ISO/IEC 15693, FeliCa, and NFC Forum digital protocol specifications. The SPI host interface runs up to 10 MHz and exposes an NCI-compliant command set, making the part portable across any OS with an NCI driver. Typical applications include payment terminals, mobile point-of-sale (mPOS) devices, access control readers, IoT pairing and provisioning, Bluetooth/Wi-Fi tap-to-connect, eTicket and transit readers, and industrial identification. The VFBGA-64 footprint suits compact reader designs where board area is at a premium. When designing in, allocate at least a 30 mm x 30 mm keep-out area under and around the antenna, route the SPI bus as short as possible, and follow NXP application note AN11740 antenna matching guidance. Use the included NXP NCI driver package to minimize stack porting effort. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the standalone NXP datasheet.
PN7160B1HN-C100E - NFC Plug & Play Controller | NXP | HVQFN-40
The NXP PN7160B1HN-C100E is a high-performance NFC Plug and Play controller with integrated firmware and an NCI (NFC Controller Interface) interface, housed in a 40-pin HVQFN exposed-pad package. Operating at 13.56 MHz and supporting FeliCa, ISO 14443, ISO 15693, and MIFARE standards, the part includes Android, Linux, and RTOS drivers for accelerated system integration across consumer and industrial platforms. The SPI host interface operates on two supply rails: 1.65 V to 1.95 V (digital host I/O) and 3 V to 3.6 V (RF analog). The /C100E firmware suffix identifies the production-ready NCI binary supplied by NXP for out-of-box interoperability with the NFC Forum stack (NCI 2.0) on Android, Linux, and Windows hosts, removing driver bring-up cost and shortening OEM time-to-market. An NFC (Near Field Communication) controller is a mixed-signal IC that drives a contactless front-end (antenna + matching network) for short-range radio at 13.56 MHz, demodulating reader/writer, peer-to-peer, and card-emulation traffic while exposing a digital command interface to a host processor. In the power-management hierarchy the PN7160 sits between the application processor and the RF antenna; it is part of the broader family of secure connectivity, contactless-payment, and identification subsystems that includes PN5180 (raw front-end only) and PN532 (legacy peer-to-peer IC). Key features include integrated firmware (no host-side stack required for basic modes), automatic ECP (Enhanced Contactless Polling) detection, low-power card-detection polling, a hardware cryptographic accelerator, secure boot, firmware update, and on-chip LDO regulators for RF and host rails. The HVQFN-40 6 mm × 6 mm footprint with exposed thermal pad supports compact reader PCB layouts while delivering high transmit output power and ISO/IEC 14443-4 higher-layer support. Operating temperature spans -25 °C to +85 °C, making the part suitable for indoor and automotive-cabin applications. Typical applications include NFC tap-to-pay terminals, access control readers, IoT commissioning nodes, smart appliance pairing, and Bluetooth/Wi-Fi hand-off access points. When designing with the PN7160B1HN, careful impedance matching of the antenna loop and TVS protection on the antenna pads are critical to meet IEC 61000-4-2 ESD requirements. Keep the 40 MHz crystal reference and its load capacitors within a few millimeters of the XIN/XOUT pins to maintain RF output stability.
PN7161A1EV-C100Y - NFC Plug & Play Controller, Apple ECP, VFBGA-64 | NXP
The NXP Semiconductors PN7161A1EV-C100Y is an NFC Plug and Play Controller with integrated firmware and NCI (NFC Controller Interface), housed in a 64-ball VFBGA package. It is a 13.56 MHz RFID reader IC supporting FeliCa, ISO 14443, ISO 15693, MIFARE, and NFC Forum protocols via an I2C host interface, supplied from a 1.65V-1.95V or 3.0V-3.6V dual-rail input. The /C100Y variant adds Apple Enhanced Contactless Polling (ECP) support on top of the standard PN7161 feature set, targeting iPhone-based wallet and access-control use cases. An NFC controller is a mixed-signal IC that handles the physical-layer (RF front-end, modulation/demodulation) and low-level protocol stack of an ISO 14443/ISO 15693 reader system, offloading these real-time tasks from the host application processor. The host communicates via NCI (a standardized command set defined by the NFC Forum) over I2C, and the PN7161 family adds integrated firmware (Plug and Play) so designers do not need to develop or certify a contactless stack themselves. This places the PN7161 in the taxonomy: NFC controller -> contactless reader -> 13.56 MHz RF IC -> wireless/RFID IC -> semiconductor. Key features include integrated RF front-end, automatic ECP polling per Apple specification, support for all major contactless standards (ISO 14443 A/B, ISO 15693, FeliCa, MIFARE Classic/Ultralight/DESFire, NFC-DEP), NCI 2.0-compliant host interface, and low-power standby/Polling loop modes. The integrated DC-to-DC control supports direct battery supply in the 2.8V-5.5V range when paired with an NXP PCA941xA companion, simplifying power-tree design in portable terminals. Architecturally, the PN7161 integrates an ARM Cortex-M0 core for on-chip firmware execution, an AGC-controlled RF transmitter, multiple receiver inputs for better small-antenna performance, and a high-efficiency PMU. Compared with discrete reader ICs, the integrated firmware removes a major certification risk and reduces time-to-market for OEM payment, access, and pairing products. Typical applications include NFC payment terminals, point-of-sale (POS) readers, access control and identity readers, Bluetooth/NFC pairing, and Apple Wallet VAS/Value-Added Services. The wide host interface and OS-agnostic NCI make it compatible with Linux, Android, Windows, and RTOS-based hosts. Design consideration: select an external DC-DC such as the PCA9410A/PCA9411A/PCA9412A when VIN exceeds 5.5V or when higher output power is required. Without a DC-DC, the part operates from a clean 1.8V or 3.3V rail. This page synthesizes distributor pricing from DigiKey/Mouser/LCSC, drop-in alternative MPNs, and practical PCB/antenna design notes not collated in the manufacturer datasheet.
PN7161A1HN - NFC Plug & Play Controller with Apple ECP | NXP
The NXP Semiconductors PN7161A1HN is a 13.56 MHz NFC Plug and Play controller with integrated firmware, NCI 1.0 host interface, and hardware support for Apple Enhanced Contactless Polling (ECP), housed in a 40-pin HVQFN exposed-pad package (6x6 mm). It supports FeliCa, ISO 14443-A/B, ISO 15693, MIFARE Classic, MIFARE DESFire, and NXP NTAG/NFC Forum Type 1-5 tag protocols through its integrated transceiver, AFE, and on-chip matching network. An NFC controller is a mixed-signal semiconductor that combines a 13.56 MHz RF front-end (transmitter, receiver, and antenna matching) with a digital protocol stack. It sits below the application processor in a connected device's architecture: host SoC -> NCI/I2C -> NFC controller -> RF field -> contactless tag/reader/P2P peer. Within the broader taxonomy the PN7161A1HN belongs to: NFC controller -> contactless front-end IC -> wireless connectivity -> semiconductor. Offloading RF and protocol handling from the host reduces BOM count, firmware effort, and EMC risk for OEMs integrating contactless features. Key features include a single supply input (1.65-3.6 V with internal DC-DC supporting 3.0-5.5 V VBAT variants on related part numbers), up to 1.5 W output power delivered to the antenna load, ultra-low-power card-detection polling modes that draw roughly 100 uA in LPCD, integrated firmware loadable over I2C, and hardware cryptographic accelerators for MIFARE Classic Crypto1 and AES-128. An exposed thermal pad keeps theta_JA low enough for handheld and POS-terminal designs without an external heatsink. The PN7161A1HN embeds an Arm Cortex-M0 core that runs the NCI framing, AFI/anti-collision, and proprietary NXP extensions. The integrated TX LDO and current-limiting circuitry protect against antenna detuning and foreign-field events, while the embedded matching network simplifies PCB antenna design - external components are limited to a single EMC filter and the antenna coil itself. Typical applications include NFC tap-to-pay terminals, smartphone and tablet accessory sidecar PCBs, Bluetooth-pairing smart speakers, POS/PIN-pad readers, eBike and EV-charging authentication, and contactless firmware-update kiosks. Apple ECP enables a deterministic contactless handshake with iOS 17+ for wallet card selection and digital car-key workflows. When designing with this part, follow NXP application note AN12364 for the recommended antenna matching network and EMC filter component values. Keep the antenna trace loop area below 1 cm² away from the IC to minimize stray coupling, and provide a low-impedance ground plane under the exposed pad using at least nine thermal vias to the inner ground layer. This page consolidates distributor pricing, verified pin-compatible alternatives from the PN7160/PN7161 family, and practical layout notes not aggregated on the manufacturer datasheet.
PN7161A1HN-C100E - NFC Plug & Play Controller with Apple ECP | NXP
The NXP Semiconductors PN7161A1HN-C100E is an NFC (Near Field Communication) Plug and Play controller with integrated firmware, an NCI (NFC Controller Interface) host interface, and native support for Apple Enhanced Contactless Polling (ECP), housed in a 40-pin HVQFN (6 mm x 6 mm) exposed-pad module. It targets a 13.56 MHz RF carrier and supports FeliCa, ISO 14443 (Type A/B), ISO 15693, MIFARE, and NFC Forum tag types, while exposing an I2C host interface at addresses selectable between 1.65V-1.95V (host) and 3.0V-3.6V (RF/PMU) supply domains. An NFC controller is a mixed-signal IC combining an RF analog front-end, a digital protocol stack (NCI 1.0 / 2.0), and an embedded firmware state machine that offloads host-side polling, anti-collision, and tag/RFID reader transactions. The PN7161 belongs to the broader NXP NFC controller family (PN5180, PN5190, PN7220, PN7150, PN7160), positioned as a drop-in upgrade for designers migrating from PN7150/PN7159 and seeking lower host CPU overhead. It is a key subcategory of RFID Reader ICs inside RF Identification, which sits in the Wireless / Sensor Network technology stack alongside Wi-Fi and BLE combo parts. Key features include full NCI 1.0/2.0 host compliance, embedded firmware for autonomous polling, Apple ECP support, support for all NFC Forum modes (Reader/Writer, Peer-to-Peer, Card Emulation), an integrated LDO/DC-DC for the RF section, and a single I2C interface. The integrated firmware reduces host code size and minimizes the need for host CPU interrupts, accelerating Linux, Android, and RTOS porting on i.MX, LPC, and Kinetis MCU platforms. The 40-pin HVQFN exposed pad also provides a low-thermal-resistance path, supporting continuous RF field generation. Architecturally, the PN7161A1HN-C100E pairs an ARM Cortex-M0 core with NXP's proven analog demodulator IP, on-chip tuning capacitors, and direct battery connection support through the integrated VANT (antenna supply) booster. This reduces external BOM (no external LDO required) and simplifies PCB layout for POS terminals, access control readers, and IoT-NFC bridges. Apple ECP authorization (NDA-gated firmware variant) requires registration with Apple MFi to enable ECP features - the silicon supports it but the firmware unlock is a software/license step. Typical applications include payment terminals (POS), physical access control readers, NFC tag readers in printers/consumer electronics, automotive infotainment NFC pairing (AEC-Q100 subscription grade not in -C100E suffix), and IoT commissioning bridges. Designers choose it over PN7150 for lower BOM, lower host CPU load, and Apple ECP readiness, and over PN5180/PN5190 when a higher-level NCI interface is preferred over a register-level PHY. When designing with this part, ensure the PCB antenna matching network targets 13.56 MHz with a Q below 35 to meet ISO 14443 bandwidth, and route the exposed thermal pad with at least 9 thermal vias to a continuous ground pour. Because the I2C SDA/SCL lines require pull-ups per the NCI specification, populate them per the typical application schematic and verify the host MCU's I2C clock-stretching tolerance - NCI polling bursts can stretch the clock longer than naive I2C controllers tolerate.
PN7161A1HN-C100Y - NFC Plug & Play Controller | NXP | 40-VFQFN
The NXP Semiconductors PN7161A1HN-C100Y is an NFC Plug and Play controller with integrated firmware and NCI (NXP NFC Controller Interface), operating at 13.56 MHz and supporting FeliCa, ISO 14443, ISO 15693, and MIFARE contactless protocols in a 40-pin HVQFN (SOT1655-1) exposed-pad package. This PN7161 variant specifically adds support for Apple ECP (Enhanced Contactless Polling), enabling seamless integration with Apple devices. The device operates from dual supply rails of 1.65V to 1.95V (typically 1.8V) and 3.0V to 3.6V for the host interface and RF analog sections respectively. The integrated firmware eliminates the need for a host-resident NFC stack, dramatically reducing host code size and design-in complexity. Host communication is handled via I²C, supporting standard MCUs from NXP's LPC, Kinetis, and i.MX families as well as third-party controllers. Background: An NFC (Near Field Communication) controller is a specialized mixed-signal IC that manages the physical and protocol layers of 13.56 MHz contactless communication, including RF field generation, demodulation, modulation, anti-collision, and cryptographic authentication for tags/cards. NFC controllers sit within the broader hierarchy of RF identification ICs -> RFID reader/transponder ICs -> wireless connectivity -> semiconductor, providing the lowest-level hardware interface while higher software layers (NCI, NFC Forum, NDEF) handle application logic. Modern plug-and-play NFC controllers integrate the full firmware stack so the host processor only needs to issue high-level commands, making them functionally distinct from RFID reader chips that require an external stack. Key features include a high RF output power supporting typical NFC reader ranges, low standby current suitable for always-on applications, support for EMVCo and NFC Forum compliance, and a single 40-pin package that consolidates all functions to minimize external BOM. The exposed thermal pad enables efficient heat dissipation in compact designs. The C100Y variant is the Apple ECP-enabled firmware configuration shipped in production packaging quantities, while the base PN7160 supports the same hardware without Apple-ECP-specific code extensions. The integrated ARM Cortex-M0 core handles all on-chip processing, offloading real-time NFC protocol timing from the application processor. An on-chip LDO and DC-DC converter generate internal supply rails from a single external 3.3V feed, simplifying power-tree design. The device also includes EEPROM for firmware patches and configuration storage, so field updates do not require external memory components. Typical applications include NFC payment terminals, Bluetooth pairing via NFC, smart home commissioning, wireless charging authentication, access control readers, and OEM authentication tags. The Apple ECP support specifically targets iPhone-based tap-to-pair and tap-to-pay use cases. When designing with this controller, follow NXP's reference antenna design guidelines and ensure proper impedance matching for the matching network components to achieve the rated RF output power across all supported protocols.
PN7161B1EV - NFC Plug & Play Controller, 13.56MHz, VFBGA-64 | NXP
The NXP Semiconductors PN7161B1EV is a Near Field Communication (NFC) Plug and Play controller with integrated firmware and NCI host interface, supporting Apple ECP and housed in a 64-pin VFBGA package. It operates at the 13.56 MHz carrier frequency and is qualified for FeliCa, ISO 14443, ISO 15693, and MIFARE protocols, enabling broad interoperability with contactless cards, tags, and peer devices. What is an NFC controller? An NFC controller is a contactless front-end IC that handles the RF physical layer, protocol stack, and (in many NXP devices) the host-side NCI interface for an application processor. NFC controllers belong to the broader category of RFID reader/writer ICs, which sit within RF & wireless identification semiconductors. They typically integrate an RF front-end, a digital protocol engine, and a host communication interface (I2C, SPI, or NCI), allowing designers to add contactless functionality without writing low-level firmware from scratch. Key features of the PN7161B1EV include support for reader/writer, peer-to-peer, and card-emulation modes; integrated NCI 1.0 host interface over SPI; an on-chip RF front-end with Tx driver and Rx chain; and an integrated firmware stack. The device supports a low-power mode to meet mobile and IoT power budgets, and includes Apple Enhanced Contactless Polling (ECP) support for iOS interoperability. The PN7161B1EV uses a 64-ball VFBGA package optimized for compact PCB layouts typical of smartphones, wearables, and IoT terminals. Internally, it combines an ARM Cortex-M0 core for firmware execution with a dedicated RF front-end, allowing the host processor to offload all NFC stack processing. This architecture reduces host CPU load and simplifies software integration for Android, Linux, and RTOS environments. Typical applications include NFC payment terminals, mobile point-of-sale (mPOS) devices, Bluetooth-pairing tags, automotive digital key systems, eGovernment / eID readers, and IoT provisioning via NFC. The combination of NCI host interface and integrated firmware makes it especially attractive for platforms running Android or Linux where Linux NCI drivers are already available. When designing with the PN7161B1EV, note that it requires an external matching network and antenna tuned to 13.56 MHz; bypass capacitors on VCC are mandatory and the exposed pad must be soldered to the ground plane for thermal dissipation and RF return. Avoid routing digital signal traces beneath the antenna area to minimize detuning. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the NXP datasheet.
PN7161B1EV-C100Y - NFC Plug & Play Controller, Apple ECP, VFBGA-64 | NXP
The NXP Semiconductors PN7161B1EV-C100Y is a near-field communication (NFC) plug-and-play controller IC that integrates all NFC functionality on-chip, including RF front-end, NCI 1.3-compliant host interface, and embedded firmware. Operating at the 13.56 MHz carrier frequency, it supports FeliCa, ISO 14443, ISO 15693, MIFARE Classic, MIFARE DESFire, and NFC-Forum tag types. The device is supplied in a 64-ball VFBGA package measuring 5.5 mm x 5.5 mm x 0.8 mm. The C100Y firmware build adds Apple's Enhanced Contactless Polling (ECP) support on top of the standard PN7161 NCI feature set. An NFC controller is a radio-frequency identification transceiver that implements the ISO/IEC 14443 and ISO/IEC 15693 contactless protocols, allowing a host processor to read/write NFC tags and emulate contactless smart cards. NFC controllers sit below the operating system NFC abstraction layer, above the antenna matching network, and within the broader category of RFID reader ICs and short-range wireless transceivers. By integrating the analog front end, protocol stack, and firmware, parts such as the PN7161 remove the need for the application MCU to handle millisecond-level RF timing. The PN7161B1 supports automatic RF output power configuration up to +15 dBm into a 50 ohm load, a host-controlled SPI interface (PN7160 also offers I2C), and integrated dynamic power control (DPC) that adjusts output power to compensate for detuned antennas. Supply domains include 1.65 V to 1.95 V (host IO) and 3.0 V to 3.6 V (RF analog), with deep-sleep current below 15 uA. The C100Y firmware extends standard PN7161 NCI polling by enabling Apple ECP, which speeds up iPhone reader interactions for payment, loyalty, and identity applications. This part fits best in point-of-sale terminals, mobile point-of-sale (mPOS) dongles, NFC-Forum peer-to-peer accessories, and smart-home commissioning hubs that must interoperate with iOS devices in addition to Android. The VFBGA-64 footprint is a low-profile package suited to space-constrained products, and the integrated firmware drastically shortens host-side development cycles compared to discrete RF front-ends. Designers do not need prior RF expertise - NXP provides reference antenna matching values and pre-tuned firmware images. Key design trade-offs include the 0.8 mm BGA pitch, which requires assembly with ENIG or ENEPIG surface finish and controlled-impedance routing, plus a separate reset logic to enter download mode for firmware updates. Because the PN7161B1 uses SPI while the PN7160 supports both SPI and I2C, verify host MCU peripherals before substituting. For Apple-only ECP readers the C100Y variant is required; the C100 base firmware omits ECP and is therefore not iOS-optimal.
PN7161B1HN-C100E - NFC Controller with NCI, Apple ECP | NXP
The NXP Semiconductors PN7161B1HN-C100E is an EMV L1 compliant Near Field Communication (NFC) controller with an NCI (NFC Controller Interface) and integrated firmware, supporting 13.56 MHz contactless operation in a 40-pin HVQFN (6x6 mm) exposed-pad package. It operates from 1.65V to 1.95V and 3.0V to 3.6V supply rails, interfaces to the host through SPI, and supports FeliCa, ISO 14443, ISO 15693, MIFARE, and NFC Forum applications with Apple Enhanced Contactless Polling (ECP) authorization. The PN7161B1HN-C100E is the production version designated by the /C100E firmware bundle, optimized for Apple Wallet and EMV L1 use cases. An NFC controller (also called an NFC front-end or NCI controller) is a semiconductor that sits between a host processor and an NFC antenna, handling the 13.56 MHz RF link, ISO protocol stack, and cryptography offload so that the application processor can speak to the reader through a standardized high-level interface (NCI). Within the system hierarchy, it sits at the interconnect layer: NFC controller -> NFC front-end -> wireless connectivity IC -> semiconductor. It enables contactless payments, ticketing, access control, and peer-to-peer data exchange without burdening the application MCU with real-time RF processing. Key features include full EMV L1 compliance, NCI 1.0 host interface, integrated firmware (PN7161B1HN/C100E bundle), Apple ECP support, automatic ECP handling for Apple Pay, automatic antenna tuning via the integrated VDD_TX driver, low-power standby mode with polling, and on-chip EMC filtering. The device supports both 1.8V and 3.3V host logic via separate supply pins (VDD_IO and VDD), simplifying integration with modern application processors without level shifters. The PN7161B1HN/C100E firmware adds turnkey EMV payment stack handling and Apple Wallet ECP behavior, dramatically reducing host-side software development. Compared to the PN7160, the PN7161 adds Apple ECP support after formal authorization. Compared to discrete RF front-ends (e.g. discrete NFC reader ICs without integrated firmware), the PN7161B1HN-C100E delivers a smaller BOM, simpler EMC compliance path, and faster time to market for payment terminals. Typical applications include point-of-sale (POS) terminals, mobile payment readers, access control readers, transit ticketing terminals, NFC-enabled IoT hubs, and Apple Pay-compatible accessory products. In each case the controller integrates seamlessly into designs that already have a host MCU running Linux, Android, or an RTOS, with NCI driver support available from NXP and mainline Android. When designing with this part, follow NXP application note AN11892 for the antenna matching network and reference the OM27160 evaluation board for the certified antenna design. Pay attention to the exposed-pad (EP) PCB land pattern for thermal dissipation and RF grounding, and verify that the host NCI driver is matched to the firmware bundle revision indicated on the top marking. This page synthesizes distributor pricing, drop-in pin-compatible NXP family alternatives, and practical design notes not found in the manufacturer datasheet.
PN7642 - NFC Reader IC with Cortex-M33 MCU & Security | NXP
The NXP Semiconductors PN7642 is a highly integrated NFC open controller that combines a high-performance NFC reader, a low-power Arm Cortex-M33 microcontroller with 180 kB of programmable flash memory, and a Common Criteria EAL6+ certified secure element, supplied in a BGA form factor (PN7642EV orderable variants). An NFC reader controller is a single-chip integration of an RF analog front end (for 13.56 MHz contactless communication), protocol firmware, and a host-processing MCU. Within the system hierarchy, it belongs to the RF & Wireless > NFC/RFID reader family: antenna driver -> NFC frontend -> NFC controller with MCU (PN7462, PN7642). By merging reader, MCU, and secure element, the PN7642 replaces the need for an extra discrete MCU and a dedicated Secure Element in the bill of materials, reducing board area and BOM cost in payment and access-control designs. Key features include the integrated Common Criteria EAL6+ certified secure element, EMVCo certification for contactless payments, support for ISO 14443 (Type A and Type B) and NFC Forum protocols, and the Arm Cortex-M33 core with 180 kB of user-programmable flash. GPIO resources include multi-function pins such as GPIO2 (PWM2 capability) and GPIO3 (PWM3 capability); when ULPCD (Ultra-Low-Power Card Detection) is used, GPIO3 must be dedicated to aborting the ULPCD function and cannot be allocated to other roles. Technically, the PN7642 pairs a high-performance NFC frontend with a customizable MCU subsystem, enabling customer firmware to implement application logic, key management, and cryptographic operations on-chip. The security toolbox addresses secure key storage, a primary requirement for payment terminals and secure access readers, and the part is supplied in a compact BGA package suitable for space-constrained embedded designs. Typical applications include EMVCo contactless payment terminals, secure access-control and identity readers, and NFC-enabled IoT devices that require both contactless connectivity and embedded security without external components. Design consideration: firmware architecture must account for pin multiplexing constraints such as GPIO3 contention with ULPCD, and designers should consult NXP design-in documents beyond the product data sheet, since detailed design-in information is distributed separately by NXP. This page synthesizes verified distributor pricing, drop-in alternative analysis, and practical design notes not found in the manufacturer datasheet.
PN7642EV/C100K - NFC Controller with Cortex-M33 MCU | NXP
The NXP Semiconductors PN7642EV/C100K is a high-performance NFC open controller that integrates an Arm Cortex-M33 microcontroller, a full NFC reader front end for 13.56 MHz contactless communication, and a hardware security subsystem in a single 64-ball VFBGA package. It operates from a 1.8 V to 3.5 V supply and supports ISO 14443-A, ISO 14443-3/4-B, ISO 15693, ISO 18092 (NFCIP-1), ISO 18000-3, MIFARE and FeliCa protocols, with host interfaces including I2C, SPI, UART and USB. An NFC controller is a specialized mixed-signal integrated circuit that modulates and demodulates 13.56 MHz RF signals and executes contactless protocol stacks. Within the system hierarchy, the PN7642 sits above discrete NFC front ends: by combining the analog NFC front end, a general-purpose MCU and a secure element on one die, it functions as a complete NFC reader system-on-chip within the connectivity layer of a terminal design. Key differentiating features include 180 kB of programmable flash memory (256 kB total memory per distributor listings), an integrated security toolbox optimized for secure key storage and cryptography, and low-power operation suited to battery-powered readers. The single-chip architecture removes the need for a separate host MCU and a discrete secure element, reducing bill-of-materials count and board area. Technically, the PN7642 combines NXP's proven NFC RF front end with an Arm Cortex-M33 CPU core, providing developer-customizable firmware on the C100 firmware version (01.00). GPIO pins with PWM capability (for example GPIO2/GPIO3 on balls E7 and D7) allow direct control of LEDs, buzzers and power switches. The datasheet also documents firmware variants C101 (02.00, pinless-download mode) and C102 (03.00) for field-upgradeable deployments. Typical applications include point-of-sale payment terminals, access-control readers, battery-powered smart locks, and industrial handheld readers. The security subsystem makes it particularly suited to payment and authentication use cases requiring cryptographic key protection. A key design consideration is the 64-ball VFBGA package: ball-grid mounting requires controlled reflow profiles and is not hand-solderable, so panel design and rework capability should be confirmed before layout. Antenna matching network design should follow the NXP PN7642 antenna design guidance for 13.56 MHz EMC performance. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
QCN9274 - Wi-Fi 7 4x4 MIMO RF Module | Qualcomm
The Qualcomm QCN9274 is a Wi-Fi 7 RF connectivity solution based on the Waiikiri platform, supporting dual-band 2.4 GHz and 5 GHz operation, 802.11be, and 4x4 MU-MIMO in a BGA-264 package. Verified distributor listings identify QCN9274 as an RF IC, while related Compex module documentation describes the QCN9274 family as an industrial-grade wireless platform. A Wi-Fi 7 radio module is a wireless networking component that combines advanced radio connectivity, multiple antenna paths, and host-system integration in one embedded platform. In the product hierarchy, QCN9274 is an RF transceiver IC or wireless connectivity module platform, not a general-purpose processor or passive RF component. Its 4x4 configuration gives the system four transmit or receive antenna paths in the cited module designs, while MU-MIMO supports simultaneous multi-user wireless communication. The verified source material identifies dual-band selectable 2.4 GHz and 5 GHz operation, Wi-Fi 7 IEEE 802.11be, up to 1376 Mbps physical data rate at 2.4 GHz, and up to 5765 Mbps at 5 GHz. The QCN9274 Waiikiri series is also described as industrial grade, distinguishing it from commercial-grade modules in the cited Compex documentation. Typical deployments include industrial access points, enterprise Wi-Fi infrastructure, gateways, embedded networking equipment, and modules requiring high-density wireless connectivity. The 4x4 MU-MIMO architecture is particularly relevant to systems handling multiple concurrent clients, where spatial multiplexing and throughput are important. For design integration, use the BGA-264 package definition and the applicable reference design rather than assuming a generic pin-compatible footprint. RF layout, antenna matching, thermal design, host interface configuration, and regulatory compliance must be validated against the manufacturer documentation and the selected module implementation. This page consolidates verified distributor identities, package information, Wi-Fi 7 feature references, and practical selection guidance. Detailed electrical ratings, pricing, pin-level definitions, and lifecycle terms that were not supplied by the verified sources are intentionally marked for data completion.
QPK3000 - Fully Integrated UWB RTLS Module | Qorvo
The Qorvo QPK3000 is a fully integrated IR-UWB (impulse-radio ultra-wideband) RTLS tag module operating at 6.5 GHz to 8 GHz, with an integrated 2.4 GHz radio for Bluetooth Low Energy and/or IEEE 802.15.4-2020 connectivity, supplied from a 2.5 V to 3.6 V rail and housed in a 20 x 20 mm castellated-edge package with 1.5 mm pitch and two state-of-the-art integrated antennas. An RTLS (Real-Time Location System) tag module is a wireless device that transmits precisely timestamped UWB pulses, allowing infrastructure anchors to calculate position with centimeter-class accuracy - far beyond what Bluetooth RSSI or Wi-Fi positioning can achieve. Within the wireless hierarchy, UWB sits alongside BLE and IEEE 802.15.4 as a short-range PHY standard, but its wide bandwidth and narrow pulses give it unique ranging precision. The QPK3000 combines both radio domains on one certified module. Key features include dual-radio operation (UWB plus BLE/802.15.4 at 2.4 GHz), guaranteed interoperability with UWB-enabled enterprise infrastructure including leading Access Points, support for the Omlox standard and coming compatibility with Cisco Spaces, and a flexible Zephyr-based software environment for custom RTLS development. The integrated antennas eliminate RF layout work. Architecturally, the module is compliant with IEEE 802.15.4-2015 (PHY and MAC layers) and IEEE 802.15.4z-2020, enabling Enhanced Ranging Frame formats. Two UARTs are provided for interfacing with peripheral devices and for terminal logging during software development, which shortens bring-up time considerably. Typical applications include asset-tracking tags for smart factories, indoor navigation badges, and drop-in UWB RTLS addition to existing products without PCB redesign. The 2.5 V to 3.6 V supply range suits direct lithium-cell or regulated 3.3 V designs. Design consideration: because the module is certified and pre-integrated, the main engineering effort shifts to firmware (Zephyr RTOS) and mechanical placement of the two integrated antennas away from metal enclosures. This page synthesizes distributor data, ecosystem compatibility details, and practical integration guidance not found in a single manufacturer datasheet.
QPM1002 - 8.5-10.5GHz GaN X-Band T/R FEM 3W | Qorvo
The Qorvo QPM1002 is a Gallium Nitride (GaN) MMIC front-end module (FEM) for X-Band radar applications covering 8.5 GHz to 10.5 GHz, integrating a T/R switch, a low-noise amplifier, and a power amplifier in a 5 x 5 mm QFN surface-mount package with over-mold encapsulant. A front-end module (FEM) is a highly integrated RF building block that sits between the antenna and the transceiver in a radar system. In an X-Band phased array radar, the FEM performs three critical functions: amplifying weak received echoes (LNA path), amplifying transmitted pulses (PA path), and switching between the two (T/R switch). Integrating all three on a single GaN-on-SiC die reduces board area, assembly variation, and lattice-spacing constraints compared to discrete multi-chip solutions. According to the Qorvo datasheet, the receive path delivers 25 dB of small-signal gain with a low noise figure of 2.2 dB, maximizing radar detection range against small targets. The transmit path provides 33 dB of small-signal gain and can deliver 3 W of saturated output power with a power-added efficiency (PAE) of 32%. The ANT port tolerates up to 2 W of input power, eliminating the need for an external limiter diode and its associated insertion loss. The module is fabricated on Qorvo's QGaN25 0.25 um GaN-on-SiC process. The high thermal conductivity die-attach, combined with the over-molded QFN package, allows reliable operation in high-temperature environments typical of airborne and ground-based phased array antennas. Typical applications include X-Band phased array radar transmit/receive (T/R) channels, marine and weather radar, and airborne surveillance systems where compact size and high power density are mandatory. Design consideration: the high power density of GaN requires a well-designed thermal path; the exposed package paddle must be soldered to a low-thermal-resistance via array in the PCB. This page synthesizes distributor sourcing data, drop-in alternative guidance, and practical design notes not found in the manufacturer datasheet.
QPM1002SR - X-Band 3W GaN T/R FEM 8.5-10.5GHz | Qorvo
The Qorvo QPM1002SR is an 8.5-10.5 GHz GaN MMIC front-end module (FEM) integrating a T/R switch, low-noise amplifier, and power amplifier in a 5 x 5 mm over-molded QFN surface-mount package. The receive path provides 25 dB of gain with a 2.2 dB noise figure, while the transmit path delivers 33 dB small-signal gain, 3 W of saturated output power, and 32% power-added efficiency (PAE). A transmit/receive module is a bidirectional RF front end that shares a single antenna between a transmitter and a receiver using a T/R switch. In the system hierarchy, it sits above individual MMIC amplifiers, combining switching, LNA, and PA functions into one module, and is a core building block of power management for radar front ends. Modules like the QPM1002 reduce component count, footprint, and assembly tolerance compared to discrete chains. Key differentiating features include the integration of three functions (switch, LNA, PA) on a single die-level module, which minimizes interconnect losses and lattice pitch. According to Qorvo, the part is fabricated on the QGaN25 0.25 um GaN-on-SiC process, whose wide bandgap supports high power density and ruggedness. The over-mold encapsulant combined with a proprietary high-thermal-conductivity die-attach allows operation in elevated-temperature environments, and the compact 5 x 5 mm footprint supports the tight lattice spacing required by X-Band phased array radar. Technically, the GaN-on-SiC construction offers superior thermal conductivity relative to GaAs, enabling higher channel temperatures to be tolerated and higher power density per millimeter of gate periphery. The 0.25 um gate length of the QGaN25 process supports X-Band frequencies with good efficiency, and the integrated T/R switch eliminates the insertion loss of an off-module circulator or switch in compact arrays. Typical applications include X-Band phased array radar transmit/receive channels, military and commercial radar front ends, and airborne or ground-based surveillance radar systems. In phased arrays, the module's small size directly determines achievable element pitch at 8.5-10.5 GHz. When designing with this module, thermal management is the primary consideration: the GaN die dissipates substantial heat at 3 W RF output, so the PCB ground vias and heat-spreading copper must be designed for the high-thermal-conductivity die-attach to work as intended. Bias sequencing and switch control timing should follow the manufacturer datasheet. This page synthesizes distributor availability, verified datasheet parameters, and practical design guidance for the QPM1002SR not consolidated in the manufacturer datasheet.
Quectel BC660K-GL-TE-B LTE Cat NB2 Module | Quectel
The Quectel BC660K-GL-TE-B is a high-performance multi-band LTE Cat NB2 (NB-IoT) module with extremely low power consumption, delivered in a compact LCC surface-mount package measuring 17.7 mm x 15.8 mm x 2.0 mm and weighing 1.8 g. It supports 3GPP LTE Cat NB2 with a maximum downlink rate of 127 Kbps and a maximum uplink rate of 158.5 Kbps across an extensive band set: B1/2/3/4/5/8/12/13/17/18/19/20/25/28/66/70/85, enabling near-global NB-IoT deployment on a single SKU. An NB-IoT (Narrowband Internet of Things) module is a low-power wide-area (LPWA) cellular transceiver defined by the 3GPP LTE Cat NB2 standard. Within the wireless communications hierarchy, it sits inside the LPWA family of cellular IoT technologies, alongside LTE Cat M1, and is optimized for applications that send small payloads infrequently while running for years on a single battery. Key features of the BC660K-GL-TE-B include the ultra-compact 17.7 mm x 15.8 mm x 2.0 mm LCC footprint for space-constrained designs, an extended operating temperature range of -40C to +85C for rugged environments, surface-mount technology (SMT) assembly suitable for high-volume automated production, and multi-band coverage for global carriers. The module's extremely low power consumption makes multi-year battery operation realistic for metering-grade devices. Technically, the BC660K-GL adopts LCC castellated-edge packaging, which provides reliable solder joints and resistance to vibration and shock, making it ideal for durable and rugged designs. Quectel documents a compatible-design migration path between the BC66/BC66-NA and BC660K-GL, allowing designers to move between NB-IoT generations on the same PCB concept with a documented compatible design manual. AT command control is shared with the BC950K-GL family via the common BC660K-GL/BC950K-GL AT Commands Manual. Typical applications include smart metering (water, gas, electricity), smart parking and bike sharing, smart city infrastructure, security and alarm systems, and asset tracking, where narrow bandwidth, deep coverage, and multi-year battery life outweigh raw throughput. Design consideration: because NB-IoT payloads are small and latency-tolerant, budget antenna selection and RF layout carefully per the Quectel BC660K-GL Reference Design and Hardware Design documents; RF matching network deviations from the reference design are the most common cause of failed carrier certification. This page synthesizes verified distributor data, the Quectel compatible-design migration path, and practical design guidance not consolidated on the manufacturer product page alone.
RAK2247 - SX1301 LoRa Concentrator mPCIe Module | RAKwireless
The RAKwireless RAK2247 is a mini-PCIe LoRa gateway concentrator module based on the Semtech SX1301 baseband processor, delivering up to 10 programmable parallel demodulation paths across 2 SX125x Tx/Rx front-end stages. Housed in a 50.95 mm × 30 mm PCI Express Mini Card form factor, the module supports US915 (and other regional ISM bands via SKU variants) and targets smart-metering fixed networks plus IoT deployments up to 500 nodes per km² in moderately interfered environments. A LoRa concentrator is a gateway-side baseband processor that turns a host embedded platform (any board exposing a free mPCIe slot) into a multi-channel LoRaWAN gateway. Within the broader wireless taxonomy the part sits at: LoRa concentrator -> LPWAN gateway module -> RF module -> IoT gateway hardware. By exploiting Semtech's chirp-spread-spectrum demodulation in parallel on 8 (or 10) channels, it allows simultaneous reception of many LoRa packets on different spreading factors and frequencies, which is the fundamental capability that distinguishes an 8-channel gateway from a single-channel peer device. Key features include: SPI or USB host interface (SKU dependent), integrated GPS receiver input for packet timestamping, +27 dBm maximum TX power through the on-board power amplifier, and a Listen-Before-Talk preamble scanner. Operating from a 3.3 V supply drawn through the mPCIe edge connector, the RAK2247 simplifies gateway prototyping because the host only needs to load the Semtech HAL / sx1301_hal library and forward IP packets to a LoRaWAN network server such as ChirpStack or TTN. Technically the SX1301 sits between two SX1257 (or SX1255) transceivers feeding an IF chain into the digital demodulation block; the chip contains 8 LoRa demodulation paths plus one FSK/GFSK path and one narrow-band channel. The host CPU offloads packet CRC, de-whitening and address filtering to the SX1301 firmware, dramatically reducing the gateway CPU load compared to a soft-modem approach. RAK2247 is a complete subsystem: the SX1301 plus front-ends, TCXO, LNA, PA, balun, GPS connector and IPEX antenna connectors are all integrated on the single mPCIe board. Typical applications include LoRaWAN indoor gateway prototypes, smart-metering aggregation gateways, industrial IoT bridges, and Helium light-hotspot builds. The 10-path parallel demodulation is the dominant selection criterion when a deployment expects concurrent traffic from many SF7–SF12 nodes. When designing with RAK2247, ensure the host carrier board routes USB D+/D- or SPI pins (CS, CLK, MOSI, MISO, IRQ, RESET) to a free mPCIe socket, supplies a clean 3.3 V at 500 mA, and provisions an IPEX antenna pigtail for the LoRa port and a separate IPEX for GPS. This page synthesizes distributor pricing, same-brand and cross-brand drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.