5CSEBA5U19C8N vs 5CSEBA5U19C7N Сравнение
Подробное сравнение бок о бок 5CSEBA5U19C8N от Intel и 5CSEBA5U19C7N от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Intel
5CSEBA5U19C8N - Cyclone V SE SoC FPGA, 85K LE, Dual ARM Cortex-A9 | Intel
5CSEBA5U19C8N ✓ АктивенСравнение характеристик
| Параметр | 5CSEBA5U19C8N | 5CSEBA5U19C7N |
|---|---|---|
| Бренд | Intel | Intel |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Активен | Активен |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $195,00 | $99,20 |
| Family | Cyclone V SE (SoC FPGA) | Cyclone V SE SoC FPGA |
| Logic Elements | 85,000 LE | 85,000 |
| Adaptive Logic Modules (ALMs) | 32,070 ALM | — |
| Embedded Memory | 3.88 Mbit | M10K + MLAB blocks, ~4,450 Kbits total |
| Processor Cores | Dual ARM Cortex-A9 MPCore | — |
| Core Maximum Frequency | 925 MHz (datasheet); 600 MHz commercial speed grade | — |
| L1 Cache (Instruction) | 2 x 32 kB | — |
| L1 Cache (Data) | 2 x 32 kB | — |
| L2 Cache | 512 kB shared | — |
| FPGA User I/Os | 66 I/O | — |
| Process Technology | 28 nm TSMC | — |
| Core Voltage | 1.1 V | — |
| Тип монтажа | Surface Mount (SMD/SMT) | Surface Mount (BGA) |
| Корпус | 484-UBGA (U19, 19x19 mm) | 484-UBGA (UBGAmobile, 19x19 mm) |
| Ball Pitch | [DATA_NEEDED: ball pitch in mm] | — |
| Рабочая температура | 0C to +85C (commercial) | 0C to +85C (commercial, junction) |
| Speed Grade | C8 (0.85 ns, commercial) | -7 (standard) |
| Статус RoHS | Compliant | — |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 800 MHz per core |
| Process Node | — | 28 nm low-power (TSMC) |
| Supply Voltage (Core) | — | 1.1 V typical |
| DSP Blocks | — | Variable-precision, 18x18 / 27x27 multipliers |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART |
| RoHS / Pb-free | — | Yes |
| Configuration Memory | — | External (active serial via HPS or FPGA) |
| Уровень MSL | — | 3 (per JEDEC J-STD-020, reflow 260C) |
| Block Pins (User I/O) | — | Approximately 66 user I/O pins |