EP20K600CF672C8N vs EP20K600CF672C6 Сравнение
Подробное сравнение бок о бок EP20K600CF672C8N от Intel и EP20K600CF672C6 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EP20K600CF672C8N | EP20K600CF672C6 |
|---|---|---|
| Бренд | Intel | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Активен | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $108,00 | $480,00 |
| Device Type | SPLD | — |
| Product Type | FPGA / programmable logic device | — |
| Family | APEX 20KC | APEX 20KC |
| Nominal Gate Capacity | 600K gates | — |
| Logic Elements or Cells | 24,320 | — |
| Macros | 2,432 | — |
| User I/O Count | 508 | — |
| Package Terminals | 652 pins | — |
| Корпус | BGA-652, 45 x 45 mm, 1.27 mm pitch | 672-ball FineLine BGA (CF672) |
| Package Description | 672-pin FC-FBGA | — |
| Напряжение питания | 1.8 V | — |
| Listed Frequency | 301.21 MHz | — |
| Propagation Delay | 1.48 ns | — |
| Fabrication Process | 0.15 µm | — |
| Рабочая температура | 0°C to 85°C | 0 °C to +85 °C (commercial) |
| Interconnect Metal | All-layer copper metal | — |
| I/O Configuration | 508 user I/O | — |
| Тип монтажа | Surface mount | — |
| Статус RoHS | unknown | Non-RoHS (legacy process) |
| REACH Status | unknown | — |
| AEC-Q100 Qualification | unknown | — |
| Configuration Method | [DATA_NEEDED: configuration memory and programming method] | SRAM-based, JTAG, EPC16/EPC2 |
| Core Current | [DATA_NEEDED: core supply current] | — |
| I/O Bank Voltage | [DATA_NEEDED: supported I/O voltage range] | — |
| Junction Temperature | [DATA_NEEDED: maximum junction temperature] | — |
| Тепловое сопротивление | [DATA_NEEDED: junction-to-ambient thermal resistance] | — |
| Typical Gate Count | — | 600,000 gates |
| Logic Elements (LEs) | — | 24,320 |
| Embedded System Blocks (ESBs) | — | 160 (each 2,048 bits) |
| Maximum Embedded RAM | — | 311,296 bits (311 kbit) |
| Maximum User I/O Pins | — | 508 |
| Package Body Size | — | 27 mm × 27 mm |
| Speed Grade | — | -6 (C6) |
| Core Voltage | — | 1.8 V |
| I/O Standards Supported | — | LVCMOS, LVTTL, HSTL, SSTL, GTL+ |
| Embedded PLLs | — | 4 |
| Process Technology | — | 0.18 µm CMOS, 6 metal layers |