EP20K600CF672C8N vs EP20K600CF672C6 Comparison
Detailed side-by-side comparison of EP20K600CF672C8N by Intel and EP20K600CF672C6 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EP20K600CF672C8N | EP20K600CF672C6 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $108.00 | $480.00 |
| Device Type | SPLD | β |
| Product Type | FPGA / programmable logic device | β |
| Family | APEX 20KC | APEX 20KC |
| Nominal Gate Capacity | 600K gates | β |
| Logic Elements or Cells | 24,320 | β |
| Macros | 2,432 | β |
| User I/O Count | 508 | β |
| Package Terminals | 652 pins | β |
| Package | BGA-652, 45 x 45 mm, 1.27 mm pitch | 672-ball FineLine BGA (CF672) |
| Package Description | 672-pin FC-FBGA | β |
| Supply Voltage | 1.8 V | β |
| Listed Frequency | 301.21 MHz | β |
| Propagation Delay | 1.48 ns | β |
| Fabrication Process | 0.15 Β΅m | β |
| Operating Temperature | 0Β°C to 85Β°C | 0 Β°C to +85 Β°C (commercial) |
| Interconnect Metal | All-layer copper metal | β |
| I/O Configuration | 508 user I/O | β |
| Mounting Type | Surface mount | β |
| RoHS Status | unknown | Non-RoHS (legacy process) |
| REACH Status | unknown | β |
| AEC-Q100 Qualification | unknown | β |
| Configuration Method | [DATA_NEEDED: configuration memory and programming method] | SRAM-based, JTAG, EPC16/EPC2 |
| Core Current | [DATA_NEEDED: core supply current] | β |
| I/O Bank Voltage | [DATA_NEEDED: supported I/O voltage range] | β |
| Junction Temperature | [DATA_NEEDED: maximum junction temperature] | β |
| Thermal Resistance | [DATA_NEEDED: junction-to-ambient thermal resistance] | β |
| Typical Gate Count | β | 600,000 gates |
| Logic Elements (LEs) | β | 24,320 |
| Embedded System Blocks (ESBs) | β | 160 (each 2,048 bits) |
| Maximum Embedded RAM | β | 311,296 bits (311 kbit) |
| Maximum User I/O Pins | β | 508 |
| Package Body Size | β | 27 mm Γ 27 mm |
| Speed Grade | β | -6 (C6) |
| Core Voltage | β | 1.8 V |
| I/O Standards Supported | β | LVCMOS, LVTTL, HSTL, SSTL, GTL+ |
| Embedded PLLs | β | 4 |
| Process Technology | β | 0.18 Β΅m CMOS, 6 metal layers |