EP910PC-35 vs EP610PC-25 Сравнение
Подробное сравнение бок о бок EP910PC-35 от Altera и EP610PC-25 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EP910PC-35 | EP610PC-25 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $8,70 | $9,75 |
| Family | Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | OT PLD, PAL-type, CMOS |
| Macrocells | 24 | — |
| I/O Pins | 24 | 20 (bidirectional, JTAG-programmable OE per macrocell) |
| Dedicated Inputs | 12 | 4 |
| Total Inputs | 36 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Counter Frequency | 37 MHz | — |
| Internal Performance Frequency | 100 MHz | — |
| Technology | CMOS, UV-erasable/OTP | CMOS, EPROM (UV-erasable) |
| Напряжение питания | 5 V | — |
| Рабочая температура | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature grade] |
| Корпус | 40-pin PDIP (Plastic DIP) | PDIP-24 (0.3 inch, through-hole) |
| Тип монтажа | Through-Hole | Through-Hole (DIP) |
| Architecture | PAL-type sum-of-products, AND/OR array | — |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | EPROM (UV-erasable), via Altera programming hardware |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | — |
| Device Family | — | Classic EPLD (EP610 series) |
| Macro Cells | — | 16 |
| Usable Gates | — | 300 |
| Propagation Delay (tpd) | — | 25 ns |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Статус RoHS | — | [DATA_NEEDED: RoHS status] |