EP910PC-35 vs EP610PC-25 比較
詳細な並列比較: EP910PC-35 メーカー: Altera および EP610PC-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP910PC-35 | EP610PC-25 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $8.70 | $9.75 |
| Family | Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | OT PLD, PAL-type, CMOS |
| Macrocells | 24 | — |
| I/O Pins | 24 | 20 (bidirectional, JTAG-programmable OE per macrocell) |
| Dedicated Inputs | 12 | 4 |
| Total Inputs | 36 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Counter Frequency | 37 MHz | — |
| Internal Performance Frequency | 100 MHz | — |
| Technology | CMOS, UV-erasable/OTP | CMOS, EPROM (UV-erasable) |
| 電源電圧 | 5 V | — |
| 動作温度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature grade] |
| パッケージ | 40-pin PDIP (Plastic DIP) | PDIP-24 (0.3 inch, through-hole) |
| 実装タイプ | Through-Hole | Through-Hole (DIP) |
| Architecture | PAL-type sum-of-products, AND/OR array | — |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | EPROM (UV-erasable), via Altera programming hardware |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | — |
| Device Family | — | Classic EPLD (EP610 series) |
| Macro Cells | — | 16 |
| Usable Gates | — | 300 |
| Propagation Delay (tpd) | — | 25 ns |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| RoHS ステータス | — | [DATA_NEEDED: RoHS status] |