EP910PC-35 vs EP610PC-25 Comparaison
Comparaison détaillée côte à côte de EP910PC-35 par Altera et EP610PC-25 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP910PC-35 | EP610PC-25 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $8,70 | $9,75 |
| Family | Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | OT PLD, PAL-type, CMOS |
| Macrocells | 24 | — |
| I/O Pins | 24 | 20 (bidirectional, JTAG-programmable OE per macrocell) |
| Dedicated Inputs | 12 | 4 |
| Total Inputs | 36 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Counter Frequency | 37 MHz | — |
| Internal Performance Frequency | 100 MHz | — |
| Technology | CMOS, UV-erasable/OTP | CMOS, EPROM (UV-erasable) |
| Tension d'alimentation | 5 V | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature grade] |
| Boîtier | 40-pin PDIP (Plastic DIP) | PDIP-24 (0.3 inch, through-hole) |
| Type de montage | Through-Hole | Through-Hole (DIP) |
| Architecture | PAL-type sum-of-products, AND/OR array | — |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | EPROM (UV-erasable), via Altera programming hardware |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | — |
| Device Family | — | Classic EPLD (EP610 series) |
| Macro Cells | — | 16 |
| Usable Gates | — | 300 |
| Propagation Delay (tpd) | — | 25 ns |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Statut RoHS | — | [DATA_NEEDED: RoHS status] |