EP910PC-35 vs EP910DC-35 Сравнение
Подробное сравнение бок о бок EP910PC-35 от Altera и EP910DC-35 от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EP910PC-35 | EP910DC-35 |
|---|---|---|
| Бренд | Altera | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $8,70 | $10,95 |
| Family | Classic EPLD | Classic EPLD EP910 |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV-Erasable CMOS PLD (PAL-type) |
| Macrocells | 24 | 24 |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| Total Inputs | 36 | 36 |
| Product Terms | 240 | 240 |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Counter Frequency | 37 MHz | — |
| Internal Performance Frequency | 100 MHz | — |
| Technology | CMOS, UV-erasable/OTP | CMOS, UV-erasable EPROM cell |
| Напряжение питания | 5 V | — |
| Рабочая температура | [DATA_NEEDED: operating temperature range] | 0 °C to +70 °C (commercial) |
| Корпус | 40-pin PDIP (Plastic DIP) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Тип монтажа | Through-Hole | — |
| Architecture | PAL-type sum-of-products, AND/OR array | PAL-type sum-of-products AND-OR array |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | JEDEC fuse map via device programmer; UV erase |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | — |
| Usable Gates | — | 900 gates |
| Propagation Delay (tpd) | — | 35 ns |
| Максимальная тактовая частота | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Статус RoHS | — | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |