EPC21LC20 vs EPC2CC20N Сравнение

Подробное сравнение бок о бок EPC21LC20 от Intel и EPC2CC20N от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.

Сравнение характеристик

Параметр EPC21LC20 EPC2CC20N
Бренд Intel Altera
Категория Memory ICs FPGA & CPLD
Статус жизненного цикла Активен NRND
Наличие In Stock In Stock
Цена за единицу (USD) $10,40 $10,85
Тип памяти Serial Configuration PROM (Flash-based, in-system programmable) —
Density 2 Mb (2,097,152 bits) [DATA_NEEDED: bitstream density in bits]
Configuration Mode Supported Serial (PS) for Altera SRAM-based LUT FPGAs —
Maximum DCLK Frequency 10 MHz —
Access Time approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure] —
Programming Interface IEEE 1149.1 (JTAG) JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster
Program/Erase Endurance 100 cycles minimum [DATA_NEEDED: confirm from datasheet] —
Operating Voltage (VCC) 3.0 V to 3.6 V (3.3 V typical) —
Standby Current [DATA_NEEDED: ICCSB value] —
Active Read Current [DATA_NEEDED: ICC active current] —
Operating Temperature (commercial) 0 °C to +70 °C (LC suffix) —
Operating Temperature (industrial) [DATA_NEEDED: -40 to +85 °C for LI variant] —
Корпус / Типоразмер 20-pin PLCC (J-lead, JEDEC MS-018) —
Тип монтажа Surface Mount (PLCC socket or solder) Surface Mount (PLCC-20 socket compatible)
Уровень MSL [DATA_NEEDED: confirm moisture sensitivity level] [DATA_NEEDED: MSL rating]
Статус RoHS [DATA_NEEDED: confirm from Altera product page] [DATA_NEEDED: RoHS compliance status]
Lead-Free (Pb-free) [DATA_NEEDED: confirm] —
Compatible FPGA Families ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) —
JTAG Boundary-Scan Compliant Yes (IEEE Std 1149.1) —
Data Width 1 bit (serial DATA output) —
Функция — Configuration device for SRAM-based LUT FPGAs
Корпус — PLCC-20
Configuration Interface — 16-bit parallel (FPP) / Passive Serial (PS)
Supply Voltage (VCC) — 3.3 V
In-System Programmable — Yes
Error Detection — 16-bit CRC on configuration frames
Configuration Modes Supported — FPP and PS (depends on host FPGA)
Cascadable — Yes (multiple EPC2 devices for larger bitstreams)
Open-Drain Status Pin — Yes (CONF_DONE / nSTATUS compatible)
Рабочая температура — [DATA_NEEDED: industrial/commercial temp range]

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