EPC21LC20 vs EPC2CC20N 比較
詳細な並列比較: EPC21LC20 メーカー: Intel および EPC2CC20N メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPC21LC20 | EPC2CC20N |
|---|---|---|
| ブランド | Intel | Altera |
| カテゴリ | Memory ICs | FPGA & CPLD |
| ライフサイクル状態 | 有効 | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.40 | $10.85 |
| メモリタイプ | Serial Configuration PROM (Flash-based, in-system programmable) | — |
| Density | 2 Mb (2,097,152 bits) | [DATA_NEEDED: bitstream density in bits] |
| Configuration Mode Supported | Serial (PS) for Altera SRAM-based LUT FPGAs | — |
| Maximum DCLK Frequency | 10 MHz | — |
| Access Time | approximately 35 ns [DATA_NEEDED: confirm exact datasheet figure] | — |
| Programming Interface | IEEE 1149.1 (JTAG) | JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster |
| Program/Erase Endurance | 100 cycles minimum [DATA_NEEDED: confirm from datasheet] | — |
| Operating Voltage (VCC) | 3.0 V to 3.6 V (3.3 V typical) | — |
| Standby Current | [DATA_NEEDED: ICCSB value] | — |
| Active Read Current | [DATA_NEEDED: ICC active current] | — |
| Operating Temperature (commercial) | 0 °C to +70 °C (LC suffix) | — |
| Operating Temperature (industrial) | [DATA_NEEDED: -40 to +85 °C for LI variant] | — |
| パッケージ / ケース | 20-pin PLCC (J-lead, JEDEC MS-018) | — |
| 実装タイプ | Surface Mount (PLCC socket or solder) | Surface Mount (PLCC-20 socket compatible) |
| MSLレベル | [DATA_NEEDED: confirm moisture sensitivity level] | [DATA_NEEDED: MSL rating] |
| RoHS ステータス | [DATA_NEEDED: confirm from Altera product page] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free (Pb-free) | [DATA_NEEDED: confirm] | — |
| Compatible FPGA Families | ACEX, APEX, Cyclone, FLEX, Mercury, Stratix (SRAM-based LUT) | — |
| JTAG Boundary-Scan Compliant | Yes (IEEE Std 1149.1) | — |
| Data Width | 1 bit (serial DATA output) | — |
| 機能 | — | Configuration device for SRAM-based LUT FPGAs |
| パッケージ | — | PLCC-20 |
| Configuration Interface | — | 16-bit parallel (FPP) / Passive Serial (PS) |
| Supply Voltage (VCC) | — | 3.3 V |
| In-System Programmable | — | Yes |
| Error Detection | — | 16-bit CRC on configuration frames |
| Configuration Modes Supported | — | FPP and PS (depends on host FPGA) |
| Cascadable | — | Yes (multiple EPC2 devices for larger bitstreams) |
| Open-Drain Status Pin | — | Yes (CONF_DONE / nSTATUS compatible) |
| 動作温度 | — | [DATA_NEEDED: industrial/commercial temp range] |