EPC2LC20NA vs EPC2LC20V Сравнение
Подробное сравнение бок о бок EPC2LC20NA от Altera и EPC2LC20V от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EPC2LC20NA | EPC2LC20V |
|---|---|---|
| Бренд | Altera | Intel |
| Категория | Memory ICs | FPGA & CPLD |
| Статус жизненного цикла | Последняя закупка | NRND |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $5,50 | $9,95 |
| Manufacturer | Altera Corporation (Intel Programmable Solutions Group) | — |
| Тип памяти | Configuration PROM (Flash-based, ISP) | — |
| Memory Density | 1.6 Mbit | — |
| Operating Voltage (VCC) | 3.3 V | 3.0 V to 3.6 V (3.3 V typ.) |
| Интерфейс | Serial (passive-serial) data output to FPGA | — |
| Programmability | In-system programmable via IEEE 1532 JTAG | — |
| Корпус | 20-pin PLCC (9x9 mm) | PLCC-20 (JEDEC MO-047) |
| Тип монтажа | Surface Mount (PLCC socket compatible) | — |
| Рабочая температура | -40C to +85C (industrial grade) | -40C to +85C (industrial) |
| Supported FPGA Families | APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, Cyclone, Mercury | — |
| JTAG Compliance | IEEE Std 1149.1 / IEEE 1532 | — |
| Configuration Mode | Passive Serial (PS) | — |
| Статус RoHS | [DATA_NEEDED: rohs status] | — |
| Daisy-Chain Support | Yes | — |
| Recommended Companion FPGA | Altera Cyclone, FLEX 10K, APEX 20K series | — |
| Product Type | — | Flash Configuration Device (FPGA configuration PROM) |
| Размер памяти | — | 1.6 Mb (1,678,336 bits) |
| Configuration Interface | — | Serial (Passive Serial) or 8-bit parallel |
| Maximum Configuration Clock | — | 10 MHz |
| Program/Erase Cycles | — | 100,000 cycles minimum |
| Data Retention | — | 20 years minimum |
| JTAG Support | — | IEEE 1149.1 Boundary Scan, in-system programmable |
| Storage Temperature | — | -65C to +150C |
| Lead-Free / RoHS | — | Lead-free (V suffix), RoHS compliant |
| Compatible FPGAs | — | Cyclone, Stratix, APEX 20K, ACEX 1K, FLEX 10K, FLEX 8000 |
| On-chip Oscillator | — | Yes (generates DCLK) |
| Configuration Time (typical) | — | Depends on FPGA bitstream length and clock mode |
| Уровень MSL | — | [DATA_NEEDED: MSL level] |