EPF10K200SRC240-2X vs EPF10K200SRC240-3N Сравнение

Подробное сравнение бок о бок EPF10K200SRC240-2X от Altera и EPF10K200SRC240-3N от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.

Altera
EPF10K200SRC240-2X EPF10K200SRC240-2X - FLEX 10K 200K Gates 9984 Cells FPGA | Altera

EPF10K200SRC240-2X - FLEX 10K 200K Gates 9984 Cells FPGA | Altera

EPF10K200SRC240-2X ⚠ Последняя закупка

Сравнение характеристик

Параметр EPF10K200SRC240-2X EPF10K200SRC240-3N
Бренд Altera Intel
Категория FPGA & CPLD FPGA & CPLD
Статус жизненного цикла Последняя закупка Obsolete
Наличие In Stock In Stock
Цена за единицу (USD) $70,05 $162,00
Series FLEX 10KS —
Family FLEX 10KE FLEX 10KE
Logic Cells 9984 —
Logic Array Blocks (LABs) 1248 1,248
Equivalent Gates 200,000 —
Embedded RAM (approx.) 98 Kbits —
User I/Os (max in family) 470 —
User I/Os (this package) 182 —
Propagation Delay 0.4 ns to 0.8 ns —
Max Internal Frequency 200 MHz —
Core Voltage (VCCINT) 2.5 V —
I/O Voltage (VCCIO) 3.3 V (banks; 5 V tolerant inputs) —
Корпус RQFP-240 (240-pin Power Quad Flat Pack, 34.6 x 34.6 mm, 0.5 mm pitch) 240-pin RQFP (Power QFP) with exposed pad, 34.6 x 34.6 mm, 0.5 mm pitch
Тип монтажа Surface Mount Surface Mount
Рабочая температура 0 C to +70 C (Commercial) 0 °C to +70 °C (Commercial)
Process Technology CMOS 0.22 µm CMOS SRAM
Configuration Method JTAG / Passive Serial (PS) SRAM-based; requires external configuration device (e.g., EPC2) for power-up loading
Boundary-Scan (JTAG) IEEE 1149.1 compliant —
Speed Grade -2X (industrial, upper-mid speed) -3 (commercial)
Lead-Free / RoHS [DATA_NEEDED: explicit lead-free status] —
Уровень MSL [DATA_NEEDED: moisture sensitivity level] —
Typical System Gates — 200,000
Logic Elements (LEs) — 9,984
Maximum Logic Elements — 9,984
Embedded Array Blocks (EABs) — 24
Maximum User RAM Bits — 98,304
User I/Os — 470 (effective); 182 user pins per RQFP-240 with the rest assigned to dedicated functions
Propagation Delay (tPD) — 0.40 ns
Internal Operating Frequency — 166.67 MHz
Core Supply Voltage — 2.5 V
MultiVolt I/O Support — 2.5 V and 3.3 V interfaces
JTAG Support — IEEE Std 1149.1 Boundary-Scan (contributes up to 31,250 gates of test logic)
Статус RoHS — [DATA_NEEDED: RoHS status]

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