EPF10K200SRC240-2X vs EPF10K200SRC240-3N 비교
다음의 상세 나란히 비교: EPF10K200SRC240-2X 제조: Altera 및 EPF10K200SRC240-3N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPF10K200SRC240-2X | EPF10K200SRC240-3N |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 최종 구매 | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $70.05 | $162.00 |
| Series | FLEX 10KS | — |
| Family | FLEX 10KE | FLEX 10KE |
| Logic Cells | 9984 | — |
| Logic Array Blocks (LABs) | 1248 | 1,248 |
| Equivalent Gates | 200,000 | — |
| Embedded RAM (approx.) | 98 Kbits | — |
| User I/Os (max in family) | 470 | — |
| User I/Os (this package) | 182 | — |
| Propagation Delay | 0.4 ns to 0.8 ns | — |
| Max Internal Frequency | 200 MHz | — |
| Core Voltage (VCCINT) | 2.5 V | — |
| I/O Voltage (VCCIO) | 3.3 V (banks; 5 V tolerant inputs) | — |
| 패키지 | RQFP-240 (240-pin Power Quad Flat Pack, 34.6 x 34.6 mm, 0.5 mm pitch) | 240-pin RQFP (Power QFP) with exposed pad, 34.6 x 34.6 mm, 0.5 mm pitch |
| 실장 유형 | Surface Mount | Surface Mount |
| 동작 온도 | 0 C to +70 C (Commercial) | 0 °C to +70 °C (Commercial) |
| Process Technology | CMOS | 0.22 µm CMOS SRAM |
| Configuration Method | JTAG / Passive Serial (PS) | SRAM-based; requires external configuration device (e.g., EPC2) for power-up loading |
| Boundary-Scan (JTAG) | IEEE 1149.1 compliant | — |
| Speed Grade | -2X (industrial, upper-mid speed) | -3 (commercial) |
| Lead-Free / RoHS | [DATA_NEEDED: explicit lead-free status] | — |
| MSL 레벨 | [DATA_NEEDED: moisture sensitivity level] | — |
| Typical System Gates | — | 200,000 |
| Logic Elements (LEs) | — | 9,984 |
| Maximum Logic Elements | — | 9,984 |
| Embedded Array Blocks (EABs) | — | 24 |
| Maximum User RAM Bits | — | 98,304 |
| User I/Os | — | 470 (effective); 182 user pins per RQFP-240 with the rest assigned to dedicated functions |
| Propagation Delay (tPD) | — | 0.40 ns |
| Internal Operating Frequency | — | 166.67 MHz |
| Core Supply Voltage | — | 2.5 V |
| MultiVolt I/O Support | — | 2.5 V and 3.3 V interfaces |
| JTAG Support | — | IEEE Std 1149.1 Boundary-Scan (contributes up to 31,250 gates of test logic) |
| RoHS 상태 | — | [DATA_NEEDED: RoHS status] |