10AS032H1F35E1HG - Arria 10 SX SoC FPGA 320K LE, 1.5GHz, 1152-FBGA
Артикул: 10AS032H1F35E1HG ✓ Активен| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $3850 | $3.850,00 |
| 10 | $3520 | $35.200,00 |
| 100 | $3180 | $318.000,00 |
| 500 | $2850 | $1.425.000,00 |
| 1.000 | $2540 | $2.540.000,00 |
10AS032H1F35E1HG Обзор
An SoC FPGA is a class of integrated circuit that combines a general-purpose processor subsystem (in this case ARM Cortex-A9) with programmable logic on a single die, providing hardware-software co-design flexibility. The Arria 10 SX sits in the mid-to-high-end of Intel's SoC FPGA portfolio, between the lower-power Cyclone V SoC and the high-performance Stratix 10 SoC, optimized for DSP-intensive and transceiver-rich applications where deterministic latency and parallel processing are required.
Key features include the 320K logic elements backed by embedded M20K memory blocks and variable-precision DSP blocks, 24 transceivers supporting multi-gigabit serial protocols, external memory interfaces for DDR4/DDR3/RLDRAM3/QDRII+, and the dual-core 1.5 GHz ARM Cortex-A9 MPCore with NEON media engine and single/double-precision floating-point unit. The device targets throughput-oriented embedded designs.
Architecturally, the Arria 10 SX uses TSMC's 20nm process and a coherent interconnect that allows the HPS and FPGA fabric to share memory through a 128-bit-wide multi-port SDRAM controller. Hardened PCI Express Gen3 controllers, hard memory controllers, and partial reconfiguration support reduce soft-logic overhead and accelerate time-to-market for designs requiring deterministic hardware acceleration alongside a software stack.
Typical applications include high-performance signal processing in radar and electronic warfare, real-time video processing pipelines, 5G baseband prototyping, test and measurement instrumentation, industrial machine vision with on-board analytics, and aerospace flight control systems where the combination of ARM Cortex-A9 user-space Linux and FPGA-fabric data-plane acceleration is essential.
When designing with this part, plan the PCB stack-up and power delivery network carefully: the 1152-FBGA package requires controlled-impedance escape routing, and the 0.8 mm (or finer) ball pitch demands microvia or HDI PCB technology. Allocate sufficient PCB layers for transceiver channels and DDR4 interfaces to maintain signal-integrity margins.
This page synthesizes distributor pricing, drop-in same-family alternatives, and practical board-design notes not found in the manufacturer datasheet alone, providing actionable information for hardware architects and procurement engineers evaluating the Arria 10 SX family.
Аналоги без доработки для 10AS032H1F35E1HG — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Варианты в этой серии
Модели той же серии, совместимые без доработки с 10AS032H1F35E1HG (тот же форм-фактор и посадочное место) — отличается по Package, DSP Blocks, Mounting Type, Transceivers, Hard Memory Controllers.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
10AS032H1F34I1HG
✅ Прямая замена✓ В наличии
$2077.26 / шт.
Открыть даташит →10AS032H1F34E1HG
✅ Прямая замена✓ В наличии
$1755 / шт.
Открыть даташит →10AS032H1F34I1SG
✅ Прямая замена ⚠️ Характеристики не проверены📋 Справочный аналог (нет в каталоге)
10AS032H1F34E1SG
✅ Прямая замена ⚠️ Характеристики не проверены📋 Справочный аналог (нет в каталоге)
10AS032H1F35E1HG Максимальные параметры и электрические характеристики
| Manufacturer | Intel (formerly Altera) |
| Series | Arria 10 SX |
| Device Type | System on Chip (SoC) FPGA |
| Logic Elements | 320K |
| Hard Processor Subsystem (HPS) | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 1.5 GHz |
| Корпус | 1152-FBGA, FC (Flip-Chip BGA), 35x35 mm |
| User I/O Count | 384 |
| Process Technology | 20nm TSMC |
| Embedded Memory | M20K blocks (variable, density per family) |
| DSP Blocks | Variable-precision DSP blocks |
| Transceivers | Multi-gigabit transceivers (up to 24 channels, family-wide) |
| External Memory Interfaces | DDR4, DDR3, RLDRAM3, QDRII+ |
| Hard Memory Controller | Yes |
| Hard PCIe | PCI Express Gen3 controllers (hard IP) |
| Partial Reconfiguration | Supported |
| Рабочая температура | Industrial / Extended grade (per part suffix) |
| Тип монтажа | Surface Mount (BGA) |
| Статус RoHS | Compliant |
| Lead-Free | Yes |
Конфигурация выводов 10AS032H1F35E1HG
| Контакт 1 | VCC — Core/IO power supply |
| Контакт 2 | GND — Common ground return |
| Контакт 3 | IO_BANK_1A — User I/O bank 1A (LVDS/CMOS) |
| Контакт 4 | IO_BANK_1B — User I/O bank 1B (LVDS/CMOS) |
| Контакт 5 | GXB_TX — Transmitter high-speed serial output |
| Контакт 6 | GXB_RX — Receiver high-speed serial input |
| Контакт 7 | REFCLK — Transceiver reference clock input |
| Контакт 8 | DDR4_DQ — DDR4 external memory interface data |
| Контакт 9 | DDR4_DQS — DDR4 data strobe |
| Контакт 10 | DDR4_A — DDR4 address signal |
| Контакт 11 | PCIe_TX — PCI Express Gen3 transmit differential pair |
| Контакт 12 | PCIe_RX — PCI Express Gen3 receive differential pair |
| Контакт 13 | HPS_GPIO — Hard Processor Subsystem general-purpose I/O |
| Контакт 14 | HPS_DDR — HPS DDR memory interface |
| Контакт 15 | JTAG_TCK — JTAG test clock |
| Контакт 16 | JTAG_TMS — JTAG test mode select |
| Контакт 17 | JTAG_TDO — JTAG test data out |
| Контакт 18 | JTAG_TDI — JTAG test data in |
| Контакт 19 | CONFIG_DONE — Configuration complete status |
| Контакт 20 | nCONFIG — Configuration start (active low) |
| Контакт 21 | NC — Not connected (no-ball) |
| Контакт 22 | NC — Not connected (no-ball) |
| Контакт 23 | NC — Not connected (no-ball) |
| Контакт 24 | NC — Not connected (no-ball) |
Типичное применение
10AS032H1F35E1HG подходит для 7 применениеs: Radar Signal Processing, 5G Baseband Prototyping, Industrial Machine Vision, Test and Measurement Instrumentation, Aerospace Flight Control, Medical Imaging Accelerator, Broadcast Video Processing.
Radar Signal Processing
The 10AS032H1F35E1HG suits radar signal processing because its 320K logic elements plus variable-precision DSP blocks deliver the throughput needed for pulse compression, MTI filtering, and CFAR detection in real time. Its dual-core 1.5 GHz ARM Cortex-A9 HPS runs the tracker and display stack while the fabric handles the data plane, avoiding PCIe bottlenecks. The 24 multi-gigabit transceivers accept direct ADC samples at typical radar IFs and the hard PCIe Gen3 controllers link to host processors. In a phased-array radar line card, this SoC FPGA reduces component count by replacing separate DSP + processor boards. Engineers should validate thermal envelopes under sustained 100% DSP utilization per Intel thermal guidelines.
Рекомендуется
5G Baseband Prototyping
For 5G baseband prototyping the 10AS032H1F35E1HG places the LDPC and Polar decoder datapaths in FPGA fabric while the dual-core ARM Cortex-A9 HPS runs L2/L3 protocol stack and OAM software. Transceivers handle CPRI/eCPRI fronthaul links up to 12.5 Gbps, and the hard PCIe Gen3 controllers provide the backhaul interface to the host CPU. Designers can iterate on 3GPP Release 16/17 features using Quartus Prime and SoC EDS without waiting for ASIC tape-out. Migration to production typically pairs this device with a custom ASIC or Stratix 10 SoC once the algorithm freezes. Validate spectrum mask compliance using the FPGA's on-chip signal monitoring.
Рекомендуется
Industrial Machine Vision
In industrial machine vision the 10AS032H1F35E1HG ingests multi-gigabit camera data via transceivers and runs convolutional neural network inference in fabric, while the ARM Cortex-A9 HPS serves the GigE Vision or USB3 Vision control plane. The 320K logic elements fit medium-complexity CNN accelerators, and the hard memory controller simplifies DDR4 buffer plumbing. Reduced inspection false-reject rates come from sub-frame latency versus CPU-only processing. For deterministic conveyor-line integration, the SoC FPGA's partial reconfiguration swaps inference models without halting the line. Estimate CNN fabric utilization with Quartus Early Power Estimator before committing to this device.
Рекомендуется
Test and Measurement Instrumentation
Test and measurement instruments use the 10AS032H1F35E1HG to capture high-speed ADC/DAC data and perform real-time DSP such as FFTs, decimation, and trigger detection. The HPS hosts the touchscreen UI, USB/LXI control plane, and SCPI command parser while the fabric executes the signal-processing pipeline. Transceivers feed oscilloscope and protocol-analyzer front ends, and PCIe Gen3 streams processed captures to host PCs. Partial reconfiguration enables multi-mode instruments that switch between PCIe, USB, and Ethernet compliance test personalities. Plan PCB layer count to maintain 25 Gbps transceiver channel margin.
Рекомендуется
Aerospace Flight Control
Aerospace flight-control applications benefit from the 10AS032H1F35E1HG's deterministic fabric, triple-redundant HPS support, and DO-254/DO-178 design artifacts available from Intel's aerospace design service partners. The dual-core 1.5 GHz ARM Cortex-A9 executes flight software while the FPGA fabric drives sensor I/O, actuator loops, and ARINC 429/MIL-STD-1553 interfaces. Industrial-grade F35 variants operate reliably in extended temperature ranges typical of avionics bays. Watchdog and lockstep execution modes enable mixed-criticality partitioning. Verify DO-254 compliance with your certifying authority before flight deployment.
Рекомендуется
Medical Imaging Accelerator
In medical imaging systems such as CT, MRI, and ultrasound the 10AS032H1F35E1HG accelerates image reconstruction (filtered back-projection, Fourier transforms) and runs the user interface on the HPS. Transceivers accept high-channel-count ADC data, and DDR4 external memory interfaces supply the bandwidth required for sinogram buffering. Designers must follow IEC 62304 and FDA cybersecurity guidance for the HPS software, and isolate patient-connected interfaces with proper creepage and clearance per IEC 60601-1. Choose medical-grade variants where available, and validate EMC performance under intended clinical environments.
Рекомендуется
Broadcast Video Processing
Broadcast video applications leverage the 10AS032H1F35E1HG for 4K/8K HEVC and AVC encode/decode pipelines, color-space conversion, and HDR tone mapping. The fabric handles macroblock-level parallelism while the dual-core ARM Cortex-A9 runs metadata extraction and ST-2110/ST-2059 control plane protocols. Transceivers deliver SMPTE 2022-6/2110 IP video ingest, and PCIe Gen3 streams to host CPUs in software-defined broadcast plants. Partial reconfiguration supports format-on-the-fly upgrades. Validate latency budgets against ST-2110 timing requirements before deploying in live workflows.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для 10AS032H1F35E1HG — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | 10AS032H1F34I1HG | 10AS032H1F34E1HG | 10AS032H1F34I1SG | 10AS032H1F34E1SG |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FBGA, FC (35x35) | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same |
| Logic Elements | 320K | 320K | 320K | 320K | 320K |
| HPS Maximum Frequency | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz |
| Speed Grade | H1 (F35) | H1 (F34) | H1 (F34) | H1 (F34) | H1 (F34) |
| Temperature Grade | Extended (E1) per suffix | Industrial (I1) | Extended (E1) | Industrial (I1) | Extended (E1) |
| Hard PCIe Gen3 | Yes | Yes | Yes | Yes | Yes |
| Process Technology | 20nm TSMC | 20nm TSMC | 20nm TSMC | 20nm TSMC | 20nm TSMC |
Ключевые отличия
- Higher HPS maximum frequency versus prior-generation SoC FPGAs (против 5ASXFB3H4F40C5N (Arria V SX))
- Smaller BGA footprint at higher logic density (против 5ASXFB3H4F40C5N (Arria V SX, 1517-FBGA))
- Drop-in industrial-temperature variant already in catalog (против 10AS032H1F34I1HG)
- Hard PCIe Gen3 controllers versus soft PCIe in lower-tier FPGAs (против Cyclone V SX SoC FPGAs)
Заметки по проектированию
The 1152-FBGA F35 package requires HDI PCB technology with microvia escape routing. Plan at least 12 PCB layers to maintain 85-ohm differential impedance for multi-gigabit transceivers and 100-ohm USB SuperSpeed pairs. Reference Intel's Arria 10 PCB design guidelines for stackup, via-in-pad recommendations, and length-matching tolerances between transceiver channels and DDR4 interfaces. Decoupling requires distributed 0402 capacitors under the package plus bulk capacitors on the back side.
Estimated: at the 20nm TSMC process corner with 320K LE fabric at 100% utilization, core power can exceed 25W; total power including HPS and transceivers commonly reaches 35-45W. The 35x35 mm F35 BGA has a junction-to-ambient thermal resistance of approximately 8 C/W with proper heatsink attachment. Use a high-performance thermal interface material and a finned heatsink with at least 50 LFM airflow to keep the junction below 100 C in industrial-temperature deployments.
Do not assume pin compatibility across F35 and F29 BGA packages - the F35 has 1152 balls while the F29 has fewer, so ball mapping differs. When migrating speed grades, update the Quartus project to load the correct timing model; mixing speed grades causes timing failures. The HPS boot configuration requires a valid bootloader on QSPI flash; do not power up with corrupt image or the HPS will fail to boot. Always release nCONFIG properly before initiating configuration.
Multi-gigabit transceiver channels require reference clock jitter below 150 fs RMS for 10 Gbps operation; use a dedicated jitter cleaner such as the Si5341 if your system clock source exceeds that budget. Pre-emphasis and de-emphasis settings from the Quartus transceiver toolkit should be tuned with your actual channel s-parameters, not defaults. For DDR4 interfaces, validate write and read leveling through the external memory interface toolkit before locking the PCB design.
Estimated: at full fabric utilization and 1.5 GHz HPS load, the 10AS032H1F35E1HG draws between 30W and 45W total. Use a multi-rail PMIC such as the LTC3615 or TPS65218 to supply core, HPS, transceiver, and I/O rails with proper sequencing (core first, then HPS, then I/O). Decoupling bulk capacitors must be placed within 25 mm of the BGA and the inductor ripple current rating must exceed the worst-case load step by 30% to avoid transient collapse.
Информация о соответствии
RoHS and lead-free compliance confirmed from Intel product page. AEC-Q100 not applicable for FPGAs (intended industrial/aerospace use). Conflict-minerals compliance per Intel supply-chain policy. Halogen-free status [DATA_NEEDED] - confirm with Intel product declaration letter.
