10AS032H2F35E2LG - Arria 10 SX 320K LE SoC FPGA | Altera / Intel
Артикул: 10AS032H2F35E2LG ✓ Активен| Кол-во | Цена за ед. | Итого |
|---|---|---|
| 1 | $3450 | $3.450,00 |
| 10 | $3120 | $31.200,00 |
| 100 | $2825 | $282.500,00 |
| 500 | $2545 | $1.272.500,00 |
| 1.000 | $2310 | $2.310.000,00 |
10AS032H2F35E2LG Обзор
What is an SoC FPGA? An SoC FPGA is a hybrid device that tightly couples a general-purpose applications processor subsystem (typically ARM Cortex-A cores with caches, MMU, and peripherals) with traditional FPGA programmable logic on a single die. Compared to a discrete FPGA + external CPU implementation, an SoC FPGA reduces board area, simplifies PCB layout, enables lower-latency interconnects between software and hardware, and offers a unified power/clock domain. The Arria 10 SX family sits in the mid- to high-performance tier of Intel's SoC FPGA portfolio, between Cyclone V/10 and the high-end Stratix 10 SoC family.
Key features include 320K adaptive logic modules (ALMs), approximately 19.4 Mb of on-chip M20K memory, hard memory controllers supporting DDR4, DDR3, LPDDR3, and QDRIV, integrated PCIe Gen2/Gen3 hard IP blocks, and up to 24 transceivers supporting rates up to 12.5 Gbps. The hard processor system runs at up to 1.5 GHz (typical) with 32 KB I-cache and 32 KB D-cache per core, NEON media engine, and a rich set of peripherals including EMAC, USB 2.0 OTG, NAND flash controller, SPI, I2C, and UART. The FPGA fabric is hardened with variable-precision DSP blocks (up to 1,518) implementing IEEE 754 single-precision floating point.
Architecturally, the Arria 10 SX uses a coherent ARM Cortex-A9 cluster connected via a 125 MHz ARM NIC-301 interconnect to the FPGA fabric on-chip. Designers boot Linux, VxWorks, or bare-metal applications on the HPS while accelerating custom logic, signal processing, and high-throughput data movement in the FPGA. The 1152-ball FCBGA (F35) package exposes the full I/O count including HPS dedicated pins, high-speed LVDS pairs, and transceiver channels for line-card, backplane, and baseband designs.
Typical applications include wireless baseband processing (LTE small cells, microwave backhaul), broadcast video encoding/decoding, radar and electronic-warfare signal chains, industrial machine vision, and embedded defense platforms requiring both deterministic real-time hardware and a Linux-capable processor. The combination of ARM Cortex-A9 software ecosystem and 320K LE fabric makes the part well suited to mid-complexity designs where a discrete processor would bottleneck data movement.
When designing with the 10AS032H2F35E2LG, ensure a multilayer PCB with at least 12 layers and controlled-impedance routing for transceivers and DDR interfaces. Thermal management is critical: at maximum fabric utilization the device can dissipate up to approximately 35 W, requiring a heatsink with at least 100 LFM airflow. Configure boot mode, MSEL, and pin multiplexing through the Quartus Prime toolchain.
This page synthesizes distributor pricing, package-level alternatives from the same Arria 10 SX family, and practical design guidance not found in the manufacturer datasheet alone, helping engineers shorten sourcing and design-in cycles.
Аналоги без доработки для 10AS032H2F35E2LG — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.
Варианты в этой серии
Модели той же серии, совместимые без доработки с 10AS032H2F35E2LG (тот же форм-фактор и посадочное место) — отличается по Package, Logic Elements, Mounting Type, Process Technology, Family.
Инструмент быстрого сравнения — выберите альтернативные компоненты для сравнения бок о бок:
10AS032H2F35E1HG
✅ Прямая замена✓ В наличии
$1293 / шт.
Открыть даташит →10AS032H1F35E1HG
✅ Прямая замена✓ В наличии
$2540 / шт.
Открыть даташит →10AS032H1F35I1HG
✅ Прямая замена✓ В наличии
$2265 / шт.
Открыть даташит →10AS032H2F35E2LG Максимальные параметры и электрические характеристики
| Family | Arria 10 SX SoC FPGA |
| Device Variant | 10AS032 (320K Logic Elements) |
| Logic Elements | 320,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Fabric Frequency | 1.5 GHz |
| Корпус | 1152-ball FCBGA (F35), 35x35 mm |
| Тип монтажа | Surface Mount (BGA) |
| Process Technology | TSMC 20 nm |
| On-chip Memory | Approx. 19.4 Mb M20K blocks |
| DSP Blocks | Up to 1,518 (variable-precision, IEEE 754 single-precision FP) |
| Hard Memory Controllers | DDR4, DDR3, LPDDR3, QDRIV |
| Transceivers | Up to 24 channels, up to 12.5 Gbps |
| PCIe Hard IP | Gen2/Gen3 |
| HPS Peripherals | EMAC, USB 2.0 OTG, NAND, SPI, I2C, UART |
| Operating Temperature Grade | E2 (Extended, -40C to +105C) |
| Статус RoHS | Compliant |
Руководство по цоколевке 10AS032H2F35E2LG в корпусе 1152-ball fcbga (f35), 35x35 mm
Цоколевка для 10AS032H2F35E2LG (корпус 1152-ball fcbga (f35), 35x35 mm). Эта цифровая ИС включает выводы GPIO, интерфейсы связи (UART, SPI, I2C) и выводы питания. Обратитесь к техническому описанию производителя для альтернативных функций выводов и вариантов конфигурации. Необходимо для проектирования встраиваемых систем и трассировки печатных плат.
Нет подробных данных о распиновке для 10AS032H2F35E2LG.
Обратитесь к даташиту для полной конфигурации выводов.
Типичное применение
10AS032H2F35E2LG подходит для 6 применениеs: Wireless Baseband Processing (LTE/5G Small Cell), Broadcast Video Encoding / Decoding, Radar and Electronic Warfare Signal Processing, Industrial Machine Vision Systems, Avionics and Defense Embedded Computing, Medical Imaging (Ultrasound / CT Front-End).
Wireless Baseband Processing (LTE/5G Small Cell)
The 10AS032H2F35E2LG is well-suited for LTE and 5G small-cell baseband processing because its 24 transceiver channels at 12.5 Gbps deliver the SERDES throughput required for CPRI/eCPRI links to remote radio heads, while the 320K logic elements and 1,518 DSP blocks can implement PHY-layer channelization, FFT/iFFT, and digital pre-distortion algorithms. The dual ARM Cortex-A9 HPS runs the Layer-2/3 stack, real-time scheduler, and OAM management, all on the same die, eliminating the latency of a discrete CPU-FPGA interconnect. Compared to a discrete FPGA + external CPU design, the SoC FPGA reduces PCB area by approximately 40 percent and cuts JESD204B/C link latency by 50-100 ns.
Рекомендуется
Broadcast Video Encoding / Decoding
The 10AS032H2F35E2LG handles broadcast-grade HEVC/H.264 encoding and decoding at resolutions up to 4K60 because its 320K logic elements and 1,518 variable-precision DSP blocks deliver the parallel processing throughput required for motion estimation, transform coding, and in-loop filtering. The dual ARM Cortex-A9 HPS runs the transport-stream stack, PSI/SI table parsing, and conditional-access logic, while the FPGA fabric accelerates the compute-intensive codec kernels. The 24 transceiver lanes support SMPTE 2022-5/6 IP-based video transport at 10 Gbps line rates, enabling multi-channel contribution feed aggregation.
Рекомендуется
Radar and Electronic Warfare Signal Processing
The 10AS032H2F35E2LG is a strong fit for radar and electronic-warfare (EW) signal chains because its hardened DSP blocks implement IEEE 754 single-precision floating-point FFTs and pulse-Doppler processing at 1.5 GHz fabric rates, while the 24 transceiver channels up to 12.5 Gbps accept direct ADC data via JESD204B/C. The dual Cortex-A9 HPS runs the threat library, mode controller, and operator interface, sharing a coherent memory space with the FPGA fabric via the on-chip interconnect. The extended E2 temperature grade (-40C to +105C) supports outdoor and shipborne deployments.
Рекомендуется
Industrial Machine Vision Systems
The 10AS032H2F35E2LG excels in industrial machine vision because its 320K logic elements and variable-precision DSP blocks implement image preprocessing (debayering, lens correction, edge detection) at line-scan rates of 100 kHz+ while the dual ARM Cortex-A9 HPS runs the classification neural network, defect detection, and PLC communication. The 12.5 Gbps transceivers support CoaXPress 2.0 and 10 GigE Vision camera links, and the hard PCIe Gen2/Gen3 controllers enable host-side frame transfer to industrial PCs. Compared to a discrete DSP + FPGA approach, the SoC FPGA simplifies software stack deployment and reduces overall system cost by approximately 25 percent.
Рекомендуется
Avionics and Defense Embedded Computing
The 10AS032H2F35E2LG is well-matched to avionics and defense embedded-computing platforms because the hardened ARM Cortex-A9 HPS runs VxWorks, INTEGRITY, or LynxOS-178 DO-178 certifiable RTOS, while the FPGA fabric implements DO-254 certifiable custom I/O, MIL-STD-1553, ARINC 429, and high-speed sensor interfaces. The E2 extended temperature grade (-40C to +105C) supports airborne and ground-vehicle environments, and the F35 1152-ball FCBGA package is rated for the shock and vibration profiles common to DO-160 testing. Compared to discrete processor + FPGA designs, the SoC FPGA halves the qualification effort for multi-core DAL-B/C certification.
Рекомендуется
Medical Imaging (Ultrasound / CT Front-End)
The 10AS032H2F35E2LG is well-suited to medical-imaging front-end signal processing because its variable-precision DSP blocks implement beamforming, FFT-based Doppler processing, and image reconstruction across 64-128 channels in real time, while the dual ARM Cortex-A9 HPS runs the user interface, DICOM stack, and patient-data management. The 12.5 Gbps transceivers accept raw ADC data from 16-channel ultrasound front-ends at sample rates up to 80 MSPS, and the DDR4 hard controllers feed large frame buffers at 25.6 GB/s. Compared to a discrete GPU-based beamformer, the SoC FPGA delivers 4-8x lower power per channel.
Рекомендуется
Сводка рекомендуемых товаров
Справочные инженерные данные для 10AS032H2F35E2LG — сравнение, рекомендации по проектированию и информация о соответствии.
Руководство по выбору
Сравнение с аналогами
| Параметр | Этот товар | 10AS032H2F35E1HG | 10AS032H1F35E1HG | 10AS032H1F35I1HG |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | 1152-ball FCBGA (F35) 35x35 mm | 1152-ball FCBGA (F35) 35x35 mm - same | 1152-ball FCBGA (F35) 35x35 mm - same | 1152-ball FCBGA (F35) 35x35 mm - same |
| Logic Elements | 320K | 320K | 320K | 320K |
| Hard Processor System | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
| Maximum Fabric Frequency | 1.5 GHz | 1.5 GHz | 1.4 GHz (H1 speed grade) | 1.4 GHz (H1 speed grade) |
| Transceivers | Up to 24 channels at 12.5 Gbps | Up to 24 at 12.5 Gbps | Up to 24 at 12.5 Gbps | Up to 24 at 12.5 Gbps |
| Temperature Grade | E2 (-40C to +105C) | E1 (0C to +100C) | E1 (0C to +100C) | I1 (-40C to +100C) |
| Approx. Unit Price (qty-1, USD) | $3,450 | $3,250 (est.) | $3,050 (est.) | $3,100 (est.) |
Ключевые отличия
- Wider operating temperature range (E2 vs E1) (против 10AS032H2F35E1HG)
- Higher H2 speed grade for tighter timing margins (против 10AS032H1F35E1HG)
- Same F35 1152-ball FCBGA package as primary alternative - PCB reuse (против 10AS032H2F35E1HG)
Заметки по проектированию
The Arria 10 SX 320 device can dissipate up to approximately 35 W at maximum fabric utilization. A heatsink with thermal resistance below 0.5 C/W and at least 100 LFM airflow is recommended for reliable operation at full transceiver duty cycle. Theta-JA for the F35 1152-ball FCBGA package is approximately 7-9 C/W with a properly mounted heatsink; without active cooling, junction temperature may exceed the 100 C operating limit within minutes of full-utilization workload.
Use at least a 12-layer PCB stack-up with controlled-impedance routing for the 12.5 Gbps transceiver channels (100-ohm differential) and DDR4 memory interfaces. The F35 package's 1.0 mm ball pitch requires microvia or stacked-via construction with 0.075 mm laser-drilled holes. AC coupling capacitors on transceiver TX lines must be placed within 5 mm of the FPGA ball; reference Intel AN 728 for full routing guidelines.
Do not assume that all Arria 10 SX 320 variants are interchangeable across the F34 and F35 packages - they are NOT drop-in compatible. F35 (35x35 mm, 1152-ball) provides the maximum I/O and transceiver count; F34 (29x29 mm, 484-ball) reduces both. Verify the PCB land pattern and full Quartus Prime pin assignment before ordering. Also confirm MSEL strap configuration (FPGA boot mode) at board bring-up; an incorrect MSEL state can render the HPS unable to boot from QSPI or SD.
DDR4 interfaces on the Arria 10 SX 320 must be routed with matched lengths within +/- 10 mils and 100-ohm differential impedance for the address/command signals. Use Intel's EMIF Toolkit in conjunction with Quartus Prime's Timing Analyzer to close timing margins. Series-termination resistors are typically NOT required because the hard memory controllers provide on-die termination; however, fly-by topology is recommended for the DDR4 clock to reduce simultaneous switching noise.
Информация о соответствии
RoHS compliant per Altera/Intel product page. AEC-Q100 not applicable - this is an industrial/commercial SoC FPGA not marketed as automotive qualified. Lead-free (Pb-free) BGA balls standard for F35 package. REACH compliance asserted by Altera/Intel. Halogen-free status [DATA_NEEDED: halogen-free certificate].
