10AS032H1F35E1HG - Arria 10 SX SoC FPGA 320K LE, 1.5GHz, 1152-FBGA
MPN: 10AS032H1F35E1HG β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3850 | $3,850.00 |
| 10 | $3520 | $35,200.00 |
| 100 | $3180 | $318,000.00 |
| 500 | $2850 | $1,425,000.00 |
| 1,000 | $2540 | $2,540,000.00 |
Drop-in alternatives for 10AS032H1F35E1HG β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
10AS032H1F34I1HG
β Drop-Inβ In Stock
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View Datasheet β10AS032H1F34E1HG
β Drop-Inβ In Stock
$1755 / Unit
View Datasheet β10AS032H1F34I1SG
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
10AS032H1F34E1SG
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
10AS032H1F35E1HG Maximum Ratings & Electrical Characteristics
| Manufacturer | Intel (formerly Altera) |
| Series | Arria 10 SX |
| Device Type | System on Chip (SoC) FPGA |
| Logic Elements | 320K |
| Hard Processor Subsystem (HPS) | Dual-core ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 1.5 GHz |
| Package | 1152-FBGA, FC (Flip-Chip BGA), 35x35 mm |
| User I/O Count | 384 |
| Process Technology | 20nm TSMC |
| Embedded Memory | M20K blocks (variable, density per family) |
| DSP Blocks | Variable-precision DSP blocks |
| Transceivers | Multi-gigabit transceivers (up to 24 channels, family-wide) |
| External Memory Interfaces | DDR4, DDR3, RLDRAM3, QDRII+ |
| Hard Memory Controller | Yes |
| Hard PCIe | PCI Express Gen3 controllers (hard IP) |
| Partial Reconfiguration | Supported |
| Operating Temperature | Industrial / Extended grade (per part suffix) |
| Mounting Type | Surface Mount (BGA) |
| RoHS Status | Compliant |
| Lead-Free | Yes |
10AS032H1F35E1HG Pin Configuration
| Pin 1 | VCC β Core/IO power supply |
| Pin 2 | GND β Common ground return |
| Pin 3 | IO_BANK_1A β User I/O bank 1A (LVDS/CMOS) |
| Pin 4 | IO_BANK_1B β User I/O bank 1B (LVDS/CMOS) |
| Pin 5 | GXB_TX β Transmitter high-speed serial output |
| Pin 6 | GXB_RX β Receiver high-speed serial input |
| Pin 7 | REFCLK β Transceiver reference clock input |
| Pin 8 | DDR4_DQ β DDR4 external memory interface data |
| Pin 9 | DDR4_DQS β DDR4 data strobe |
| Pin 10 | DDR4_A β DDR4 address signal |
| Pin 11 | PCIe_TX β PCI Express Gen3 transmit differential pair |
| Pin 12 | PCIe_RX β PCI Express Gen3 receive differential pair |
| Pin 13 | HPS_GPIO β Hard Processor Subsystem general-purpose I/O |
| Pin 14 | HPS_DDR β HPS DDR memory interface |
| Pin 15 | JTAG_TCK β JTAG test clock |
| Pin 16 | JTAG_TMS β JTAG test mode select |
| Pin 17 | JTAG_TDO β JTAG test data out |
| Pin 18 | JTAG_TDI β JTAG test data in |
| Pin 19 | CONFIG_DONE β Configuration complete status |
| Pin 20 | nCONFIG β Configuration start (active low) |
| Pin 21 | NC β Not connected (no-ball) |
| Pin 22 | NC β Not connected (no-ball) |
| Pin 23 | NC β Not connected (no-ball) |
| Pin 24 | NC β Not connected (no-ball) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS032H1F35E1HG is suitable for 7 applications: Radar Signal Processing, 5G Baseband Prototyping, Industrial Machine Vision, Test and Measurement Instrumentation, Aerospace Flight Control, Medical Imaging Accelerator, Broadcast Video Processing.
Radar Signal Processing
The 10AS032H1F35E1HG suits radar signal processing because its 320K logic elements plus variable-precision DSP blocks deliver the throughput needed for pulse compression, MTI filtering, and CFAR detection in real time. Its dual-core 1.5 GHz ARM Cortex-A9 HPS runs the tracker and display stack while the fabric handles the data plane, avoiding PCIe bottlenecks. The 24 multi-gigabit transceivers accept direct ADC samples at typical radar IFs and the hard PCIe Gen3 controllers link to host processors. In a phased-array radar line card, this SoC FPGA reduces component count by replacing separate DSP + processor boards. Engineers should validate thermal envelopes under sustained 100% DSP utilization per Intel thermal guidelines.
Recommended
5G Baseband Prototyping
For 5G baseband prototyping the 10AS032H1F35E1HG places the LDPC and Polar decoder datapaths in FPGA fabric while the dual-core ARM Cortex-A9 HPS runs L2/L3 protocol stack and OAM software. Transceivers handle CPRI/eCPRI fronthaul links up to 12.5 Gbps, and the hard PCIe Gen3 controllers provide the backhaul interface to the host CPU. Designers can iterate on 3GPP Release 16/17 features using Quartus Prime and SoC EDS without waiting for ASIC tape-out. Migration to production typically pairs this device with a custom ASIC or Stratix 10 SoC once the algorithm freezes. Validate spectrum mask compliance using the FPGA's on-chip signal monitoring.
Recommended
Industrial Machine Vision
In industrial machine vision the 10AS032H1F35E1HG ingests multi-gigabit camera data via transceivers and runs convolutional neural network inference in fabric, while the ARM Cortex-A9 HPS serves the GigE Vision or USB3 Vision control plane. The 320K logic elements fit medium-complexity CNN accelerators, and the hard memory controller simplifies DDR4 buffer plumbing. Reduced inspection false-reject rates come from sub-frame latency versus CPU-only processing. For deterministic conveyor-line integration, the SoC FPGA's partial reconfiguration swaps inference models without halting the line. Estimate CNN fabric utilization with Quartus Early Power Estimator before committing to this device.
Recommended
Test and Measurement Instrumentation
Test and measurement instruments use the 10AS032H1F35E1HG to capture high-speed ADC/DAC data and perform real-time DSP such as FFTs, decimation, and trigger detection. The HPS hosts the touchscreen UI, USB/LXI control plane, and SCPI command parser while the fabric executes the signal-processing pipeline. Transceivers feed oscilloscope and protocol-analyzer front ends, and PCIe Gen3 streams processed captures to host PCs. Partial reconfiguration enables multi-mode instruments that switch between PCIe, USB, and Ethernet compliance test personalities. Plan PCB layer count to maintain 25 Gbps transceiver channel margin.
Recommended
Aerospace Flight Control
Aerospace flight-control applications benefit from the 10AS032H1F35E1HG's deterministic fabric, triple-redundant HPS support, and DO-254/DO-178 design artifacts available from Intel's aerospace design service partners. The dual-core 1.5 GHz ARM Cortex-A9 executes flight software while the FPGA fabric drives sensor I/O, actuator loops, and ARINC 429/MIL-STD-1553 interfaces. Industrial-grade F35 variants operate reliably in extended temperature ranges typical of avionics bays. Watchdog and lockstep execution modes enable mixed-criticality partitioning. Verify DO-254 compliance with your certifying authority before flight deployment.
Recommended
Medical Imaging Accelerator
In medical imaging systems such as CT, MRI, and ultrasound the 10AS032H1F35E1HG accelerates image reconstruction (filtered back-projection, Fourier transforms) and runs the user interface on the HPS. Transceivers accept high-channel-count ADC data, and DDR4 external memory interfaces supply the bandwidth required for sinogram buffering. Designers must follow IEC 62304 and FDA cybersecurity guidance for the HPS software, and isolate patient-connected interfaces with proper creepage and clearance per IEC 60601-1. Choose medical-grade variants where available, and validate EMC performance under intended clinical environments.
Recommended
Broadcast Video Processing
Broadcast video applications leverage the 10AS032H1F35E1HG for 4K/8K HEVC and AVC encode/decode pipelines, color-space conversion, and HDR tone mapping. The fabric handles macroblock-level parallelism while the dual-core ARM Cortex-A9 runs metadata extraction and ST-2110/ST-2059 control plane protocols. Transceivers deliver SMPTE 2022-6/2110 IP video ingest, and PCIe Gen3 streams to host CPUs in software-defined broadcast plants. Partial reconfiguration supports format-on-the-fly upgrades. Validate latency budgets against ST-2110 timing requirements before deploying in live workflows.
Recommended
Recommended Products Summary
Engineering reference data for 10AS032H1F35E1HG β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS032H1F34I1HG | 10AS032H1F34E1HG | 10AS032H1F34I1SG | 10AS032H1F34E1SG |
|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel |
| Package | 1152-FBGA, FC (35x35) | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same | 1152-FBGA, FC (35x35) - same |
| Logic Elements | 320K | 320K | 320K | 320K | 320K |
| HPS Maximum Frequency | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz | 1.5 GHz |
| Speed Grade | H1 (F35) | H1 (F34) | H1 (F34) | H1 (F34) | H1 (F34) |
| Temperature Grade | Extended (E1) per suffix | Industrial (I1) | Extended (E1) | Industrial (I1) | Extended (E1) |
| Hard PCIe Gen3 | Yes | Yes | Yes | Yes | Yes |
| Process Technology | 20nm TSMC | 20nm TSMC | 20nm TSMC | 20nm TSMC | 20nm TSMC |
| Approximate Unit Price (USD, 100-piece) | $3,180 | $3,180 [DATA_NEEDED: current] | $3,180 [DATA_NEEDED: current] | $3,180 [DATA_NEEDED: current] | $3,180 [DATA_NEEDED: current] |
Key Differentiators
- Higher HPS maximum frequency versus prior-generation SoC FPGAs (vs 5ASXFB3H4F40C5N (Arria V SX))
- Smaller BGA footprint at higher logic density (vs 5ASXFB3H4F40C5N (Arria V SX, 1517-FBGA))
- Drop-in industrial-temperature variant already in catalog (vs 10AS032H1F34I1HG)
- Hard PCIe Gen3 controllers versus soft PCIe in lower-tier FPGAs (vs Cyclone V SX SoC FPGAs)
Design Notes
The 1152-FBGA F35 package requires HDI PCB technology with microvia escape routing. Plan at least 12 PCB layers to maintain 85-ohm differential impedance for multi-gigabit transceivers and 100-ohm USB SuperSpeed pairs. Reference Intel's Arria 10 PCB design guidelines for stackup, via-in-pad recommendations, and length-matching tolerances between transceiver channels and DDR4 interfaces. Decoupling requires distributed 0402 capacitors under the package plus bulk capacitors on the back side.
Estimated: at the 20nm TSMC process corner with 320K LE fabric at 100% utilization, core power can exceed 25W; total power including HPS and transceivers commonly reaches 35-45W. The 35x35 mm F35 BGA has a junction-to-ambient thermal resistance of approximately 8 C/W with proper heatsink attachment. Use a high-performance thermal interface material and a finned heatsink with at least 50 LFM airflow to keep the junction below 100 C in industrial-temperature deployments.
Do not assume pin compatibility across F35 and F29 BGA packages - the F35 has 1152 balls while the F29 has fewer, so ball mapping differs. When migrating speed grades, update the Quartus project to load the correct timing model; mixing speed grades causes timing failures. The HPS boot configuration requires a valid bootloader on QSPI flash; do not power up with corrupt image or the HPS will fail to boot. Always release nCONFIG properly before initiating configuration.
Multi-gigabit transceiver channels require reference clock jitter below 150 fs RMS for 10 Gbps operation; use a dedicated jitter cleaner such as the Si5341 if your system clock source exceeds that budget. Pre-emphasis and de-emphasis settings from the Quartus transceiver toolkit should be tuned with your actual channel s-parameters, not defaults. For DDR4 interfaces, validate write and read leveling through the external memory interface toolkit before locking the PCB design.
Estimated: at full fabric utilization and 1.5 GHz HPS load, the 10AS032H1F35E1HG draws between 30W and 45W total. Use a multi-rail PMIC such as the LTC3615 or TPS65218 to supply core, HPS, transceiver, and I/O rails with proper sequencing (core first, then HPS, then I/O). Decoupling bulk capacitors must be placed within 25 mm of the BGA and the inductor ripple current rating must exceed the worst-case load step by 30% to avoid transient collapse.
Compliance Information
RoHS and lead-free compliance confirmed from Intel product page. AEC-Q100 not applicable for FPGAs (intended industrial/aerospace use). Conflict-minerals compliance per Intel supply-chain policy. Halogen-free status [DATA_NEEDED] - confirm with Intel product declaration letter.
