10AS032H2F35E2LG - Arria 10 SX 320K LE SoC FPGA | Altera / Intel
MPN: 10AS032H2F35E2LG ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $3450 | $3,450.00 |
| 10 | $3120 | $31,200.00 |
| 100 | $2825 | $282,500.00 |
| 500 | $2545 | $1,272,500.00 |
| 1,000 | $2310 | $2,310,000.00 |
Drop-in alternatives for 10AS032H2F35E2LG — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
10AS032H2F35E1HG
✅ Drop-In✓ In Stock
$1293 / Unit
View Datasheet →10AS032H1F35E1HG
✅ Drop-In✓ In Stock
$2540 / Unit
View Datasheet →10AS032H1F35I1HG
✅ Drop-In✓ In Stock
$2265 / Unit
View Datasheet →10AS032H2F35E2LG Maximum Ratings & Electrical Characteristics
| Family | Arria 10 SX SoC FPGA |
| Device Variant | 10AS032 (320K Logic Elements) |
| Logic Elements | 320,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight |
| Maximum Fabric Frequency | 1.5 GHz |
| Package | 1152-ball FCBGA (F35), 35x35 mm |
| Mounting Type | Surface Mount (BGA) |
| Process Technology | TSMC 20 nm |
| On-chip Memory | Approx. 19.4 Mb M20K blocks |
| DSP Blocks | Up to 1,518 (variable-precision, IEEE 754 single-precision FP) |
| Hard Memory Controllers | DDR4, DDR3, LPDDR3, QDRIV |
| Transceivers | Up to 24 channels, up to 12.5 Gbps |
| PCIe Hard IP | Gen2/Gen3 |
| HPS Peripherals | EMAC, USB 2.0 OTG, NAND, SPI, I2C, UART |
| Operating Temperature Grade | E2 (Extended, -40C to +105C) |
| RoHS Status | Compliant |
10AS032H2F35E2LG 1152-ball fcbga (f35), 35x35 mm Pin Configuration Guide
Complete pinout information for 10AS032H2F35E2LG (1152-ball fcbga (f35), 35x35 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for 10AS032H2F35E2LG.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
10AS032H2F35E2LG is suitable for 6 applications: Wireless Baseband Processing (LTE/5G Small Cell), Broadcast Video Encoding / Decoding, Radar and Electronic Warfare Signal Processing, Industrial Machine Vision Systems, Avionics and Defense Embedded Computing, Medical Imaging (Ultrasound / CT Front-End).
Wireless Baseband Processing (LTE/5G Small Cell)
The 10AS032H2F35E2LG is well-suited for LTE and 5G small-cell baseband processing because its 24 transceiver channels at 12.5 Gbps deliver the SERDES throughput required for CPRI/eCPRI links to remote radio heads, while the 320K logic elements and 1,518 DSP blocks can implement PHY-layer channelization, FFT/iFFT, and digital pre-distortion algorithms. The dual ARM Cortex-A9 HPS runs the Layer-2/3 stack, real-time scheduler, and OAM management, all on the same die, eliminating the latency of a discrete CPU-FPGA interconnect. Compared to a discrete FPGA + external CPU design, the SoC FPGA reduces PCB area by approximately 40 percent and cuts JESD204B/C link latency by 50-100 ns.
Recommended
Broadcast Video Encoding / Decoding
The 10AS032H2F35E2LG handles broadcast-grade HEVC/H.264 encoding and decoding at resolutions up to 4K60 because its 320K logic elements and 1,518 variable-precision DSP blocks deliver the parallel processing throughput required for motion estimation, transform coding, and in-loop filtering. The dual ARM Cortex-A9 HPS runs the transport-stream stack, PSI/SI table parsing, and conditional-access logic, while the FPGA fabric accelerates the compute-intensive codec kernels. The 24 transceiver lanes support SMPTE 2022-5/6 IP-based video transport at 10 Gbps line rates, enabling multi-channel contribution feed aggregation.
Recommended
Radar and Electronic Warfare Signal Processing
The 10AS032H2F35E2LG is a strong fit for radar and electronic-warfare (EW) signal chains because its hardened DSP blocks implement IEEE 754 single-precision floating-point FFTs and pulse-Doppler processing at 1.5 GHz fabric rates, while the 24 transceiver channels up to 12.5 Gbps accept direct ADC data via JESD204B/C. The dual Cortex-A9 HPS runs the threat library, mode controller, and operator interface, sharing a coherent memory space with the FPGA fabric via the on-chip interconnect. The extended E2 temperature grade (-40C to +105C) supports outdoor and shipborne deployments.
Recommended
Industrial Machine Vision Systems
The 10AS032H2F35E2LG excels in industrial machine vision because its 320K logic elements and variable-precision DSP blocks implement image preprocessing (debayering, lens correction, edge detection) at line-scan rates of 100 kHz+ while the dual ARM Cortex-A9 HPS runs the classification neural network, defect detection, and PLC communication. The 12.5 Gbps transceivers support CoaXPress 2.0 and 10 GigE Vision camera links, and the hard PCIe Gen2/Gen3 controllers enable host-side frame transfer to industrial PCs. Compared to a discrete DSP + FPGA approach, the SoC FPGA simplifies software stack deployment and reduces overall system cost by approximately 25 percent.
Recommended
Avionics and Defense Embedded Computing
The 10AS032H2F35E2LG is well-matched to avionics and defense embedded-computing platforms because the hardened ARM Cortex-A9 HPS runs VxWorks, INTEGRITY, or LynxOS-178 DO-178 certifiable RTOS, while the FPGA fabric implements DO-254 certifiable custom I/O, MIL-STD-1553, ARINC 429, and high-speed sensor interfaces. The E2 extended temperature grade (-40C to +105C) supports airborne and ground-vehicle environments, and the F35 1152-ball FCBGA package is rated for the shock and vibration profiles common to DO-160 testing. Compared to discrete processor + FPGA designs, the SoC FPGA halves the qualification effort for multi-core DAL-B/C certification.
Recommended
Medical Imaging (Ultrasound / CT Front-End)
The 10AS032H2F35E2LG is well-suited to medical-imaging front-end signal processing because its variable-precision DSP blocks implement beamforming, FFT-based Doppler processing, and image reconstruction across 64-128 channels in real time, while the dual ARM Cortex-A9 HPS runs the user interface, DICOM stack, and patient-data management. The 12.5 Gbps transceivers accept raw ADC data from 16-channel ultrasound front-ends at sample rates up to 80 MSPS, and the DDR4 hard controllers feed large frame buffers at 25.6 GB/s. Compared to a discrete GPU-based beamformer, the SoC FPGA delivers 4-8x lower power per channel.
Recommended
Recommended Products Summary
Engineering reference data for 10AS032H2F35E2LG — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | 10AS032H2F35E1HG | 10AS032H1F35E1HG | 10AS032H1F35I1HG |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | 1152-ball FCBGA (F35) 35x35 mm | 1152-ball FCBGA (F35) 35x35 mm - same | 1152-ball FCBGA (F35) 35x35 mm - same | 1152-ball FCBGA (F35) 35x35 mm - same |
| Logic Elements | 320K | 320K | 320K | 320K |
| Hard Processor System | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 | Dual ARM Cortex-A9 |
| Maximum Fabric Frequency | 1.5 GHz | 1.5 GHz | 1.4 GHz (H1 speed grade) | 1.4 GHz (H1 speed grade) |
| Transceivers | Up to 24 channels at 12.5 Gbps | Up to 24 at 12.5 Gbps | Up to 24 at 12.5 Gbps | Up to 24 at 12.5 Gbps |
| Temperature Grade | E2 (-40C to +105C) | E1 (0C to +100C) | E1 (0C to +100C) | I1 (-40C to +100C) |
| Approx. Unit Price (qty-1, USD) | $3,450 | $3,250 (est.) | $3,050 (est.) | $3,100 (est.) |
Key Differentiators
- Wider operating temperature range (E2 vs E1) (vs 10AS032H2F35E1HG)
- Higher H2 speed grade for tighter timing margins (vs 10AS032H1F35E1HG)
- Same F35 1152-ball FCBGA package as primary alternative - PCB reuse (vs 10AS032H2F35E1HG)
Design Notes
The Arria 10 SX 320 device can dissipate up to approximately 35 W at maximum fabric utilization. A heatsink with thermal resistance below 0.5 C/W and at least 100 LFM airflow is recommended for reliable operation at full transceiver duty cycle. Theta-JA for the F35 1152-ball FCBGA package is approximately 7-9 C/W with a properly mounted heatsink; without active cooling, junction temperature may exceed the 100 C operating limit within minutes of full-utilization workload.
Use at least a 12-layer PCB stack-up with controlled-impedance routing for the 12.5 Gbps transceiver channels (100-ohm differential) and DDR4 memory interfaces. The F35 package's 1.0 mm ball pitch requires microvia or stacked-via construction with 0.075 mm laser-drilled holes. AC coupling capacitors on transceiver TX lines must be placed within 5 mm of the FPGA ball; reference Intel AN 728 for full routing guidelines.
Do not assume that all Arria 10 SX 320 variants are interchangeable across the F34 and F35 packages - they are NOT drop-in compatible. F35 (35x35 mm, 1152-ball) provides the maximum I/O and transceiver count; F34 (29x29 mm, 484-ball) reduces both. Verify the PCB land pattern and full Quartus Prime pin assignment before ordering. Also confirm MSEL strap configuration (FPGA boot mode) at board bring-up; an incorrect MSEL state can render the HPS unable to boot from QSPI or SD.
DDR4 interfaces on the Arria 10 SX 320 must be routed with matched lengths within +/- 10 mils and 100-ohm differential impedance for the address/command signals. Use Intel's EMIF Toolkit in conjunction with Quartus Prime's Timing Analyzer to close timing margins. Series-termination resistors are typically NOT required because the hard memory controllers provide on-die termination; however, fly-by topology is recommended for the DDR4 clock to reduce simultaneous switching noise.
Compliance Information
RoHS compliant per Altera/Intel product page. AEC-Q100 not applicable - this is an industrial/commercial SoC FPGA not marketed as automotive qualified. Lead-free (Pb-free) BGA balls standard for F35 package. REACH compliance asserted by Altera/Intel. Halogen-free status [DATA_NEEDED: halogen-free certificate].
