Intel

EPM3128ATC100-5 - MAX 3000A CPLD, 128 Macrocells, 5ns TQFP-100

Артикул: EPM3128ATC100-5 ✗ Снят с производства

В наличии Отправка в течение 1–3 рабочих дней

3.3 V Vdss 100-pin TQFP (Fine Line) Package 192.3 MHz Speed EEPROM Memory

От $15.43 USD / шт.

MOQ: 1 |

Цена обновлена: 2026-09-12

Оптовые цены

Кол-во	Цена за ед.	Итого
1	$24.12	$24,12
10	$21.7	$217,00
100	$19.29	$1.929,00
500	$17.36	$8.680,00
1.000	$15.43	$15.430,00

ℹ️ Все цены указаны в USD

Открыть datasheet (PDF) Смотреть аналоги

Количество

EPM3128ATC100-5 Обзор

The Intel (formerly Altera) EPM3128ATC100-5 is a high-performance, low-cost CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 3000A family, delivering 128 macrocells, 80 user I/Os, and a 5 ns pin-to-pin propagation delay in a 100-pin TQFP package. The device operates from a 3.3 V supply and supports 3.3-V in-system programmability (ISP) compliant with the IEEE Std. 1532 specification, enabling concurrent ISP across multi-vendor PLD platforms.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks interconnected by a programmable switch matrix. CPLDs sit between simple SPLDs and FPGAs in the programmable logic hierarchy - they offer deterministic timing (fixed pin-to-pin delays), instant-on operation from EEPROM configuration memory, and higher logic density than discrete PAL/GAL devices while consuming less power and providing more predictable timing than most FPGAs. The MAX architecture integrates logic array blocks (LABs), an interconnect matrix, I/O control blocks, and the in-system programming engine into a single CMOS die.

Key features of the EPM3128ATC100-5 include 2,500 usable gates, 80 programmable I/O pins (each configurable as input, output, or bidirectional), four dedicated input pins, a global clear signal, and output drivers programmable for 2.5 V or 3.3 V while all inputs are 2.5 V, 3.3 V, and 5.0 V tolerant. The device supports JTAG boundary-scan testing per IEEE Std. 1149.1, has programmable security bits for design protection, and provides a typical counter frequency of 192.3 MHz. The commercial temperature grade spans 0 °C to 70 °C, and the TQFP-100 package offers a low-profile surface-mount footprint suited to high-density PCB designs.

Typical applications for the EPM3128ATC100-5 include bus interface bridging (e.g., PCI-to-ISA glue logic), address decoding and chip-select generation, state-machine and sequencer implementation, I/O expansion and level translation between 5 V and 3.3 V domains, and glue-logic replacement of discrete 74-series TTL parts. It is widely used in industrial controllers, telecom base-station control boards, and legacy design refreshes where deterministic timing, instant-on behavior, and in-field reprogrammability are required.

When designing with this device, allocate sufficient decoupling (0.1 µF per supply pin), observe the IEEE 1149.1 JTAG chain if multiple devices share the bus, and confirm Quartus II / MAX+PLUS II software support for the -5 speed grade. The 'A' suffix denotes the enhanced MAX 3000A family; the -5 suffix indicates the 7.5 ns (or 5 ns commercial) speed grade, which is the slowest of the MAX 3000A speed grades.

Аналоги без доработки для EPM3128ATC100-5 — тот же корпус, pin-to-pin совместимость. Компоненты в других корпусах, требующие переработки PCB, исключены.

Варианты в этой серии

Модели той же серии, совместимые без доработки с EPM3128ATC100-5 (тот же форм-фактор и посадочное место) — отличается по Package, Operating Temperature, Propagation Delay (tPD), Usable Gates, Configuration Memory.

EPM3128ATC100-10

Altera

Package: 100-pin TQFP

Operating Temperature: 0 C to 70 C (commercial)

Propagation Delay (tPD): 10 ns

Сравнить с EPM3128ATC100-5 →

EPM3128ATC100-10N

Altera

Package: 100-pin TQFP (14 x 14 x 1.0 mm)

Operating Temperature: 0 °C to +70 °C (commercial)

Propagation Delay (tPD): 10 ns

Сравнить с EPM3128ATC100-5 →

EPM3128ATC100-10NS

Intel

Package: TQFP-100

Configuration Memory: EEPROM (non-volatile)

Сравнить с EPM3128ATC100-5 →

EPM3128ATC100-5N

Intel

Package: TQFP-100 (TC100)

Operating Temperature: 0 C to +70 C (commercial)

Propagation Delay (tPD): 5 ns

Сравнить с EPM3128ATC100-5 →

EPM3128ATC100-7

Intel

Package: 100-pin TQFP, 14x14 mm, 0.5 mm pitch

Operating Temperature: 0C to +70C (Commercial)

Propagation Delay (tPD): 7.5 ns

Сравнить с EPM3128ATC100-5 →

EPM3128ATC144-5

Altera

Package: TQFP-144 (Plastic, 1.0 mm pitch, 22x22 mm)

Operating Temperature: 0C to +70C (Commercial)

Propagation Delay (tPD): 7.5 ns

Сравнить с EPM3128ATC100-5 →

EPM3128ATI100-10

Altera

Package: TQFP-100 (1.0 mm pitch, 14x14 mm)

Operating Temperature: -40 °C to +85 °C (industrial)

Сравнить с EPM3128ATC100-5 →

✅ Прямая замена

Intel

📦 TQFP-100

MAX 3000A · CPLD (Complex Programmable Logic Device) · 128 · 8 (16 macrocells each) · Up to 10,000 · 80 · 5 ns · 192.3 MHz

✓ В наличии

$8.2 / шт.

Открыть даташит →

EPM3128ATC100-5 Максимальные параметры и электрические характеристики

Series	MAX 3000A
Family	CPLD - MAX 3000A
Macrocells	128
Usable Gates	2,500
User I/Os	80
Dedicated Inputs	4
Pin-to-Pin Delay (tpd)	5 ns (commercial); 7.5 ns
Maximum Frequency (fCNT)	192.3 MHz
Supply Voltage (VCCINT/VCCIO)	3.3 V
Output Drive Voltage	2.5 V or 3.3 V (programmable)
Input Tolerance	2.5 V, 3.3 V, 5.0 V tolerant
Program Memory Type	EEPROM
In-System Programmability	Yes, IEEE Std. 1532 compliant
JTAG Boundary Scan	Yes, IEEE Std. 1149.1
Рабочая температура	0 °C to 70 °C (Commercial)
Корпус	100-pin TQFP (Fine Line)
Тип монтажа	Surface Mount
Logic Family	CMOS
Process Technology	CMOS EEPROM

Конфигурация выводов EPM3128ATC100-5

Контакт 1	I/O — User I/O pin (pin numbers and assignments per MAX 3000A datasheet TQFP-100 pin table)
Контакт 2	I/O — User I/O pin
Контакт 3	I/O — User I/O pin
Контакт 4	I/O — User I/O pin
Контакт 5	I/O — User I/O pin
Контакт 6	I/O — User I/O pin
Контакт 7	I/O — User I/O pin
Контакт 8	I/O — User I/O pin
Контакт 9	I/O — User I/O pin
Контакт 10	I/O — User I/O pin
Контакт 11	GND — Ground
Контакт 12	I/O — User I/O pin
Контакт 13	I/O — User I/O pin
Контакт 14	I/O — User I/O pin
Контакт 15	I/O — User I/O pin
Контакт 16	I/O — User I/O pin
Контакт 17	I/O — User I/O pin
Контакт 18	I/O — User I/O pin
Контакт 19	I/O — User I/O pin
Контакт 20	I/O — User I/O pin
Контакт 21	VCCIO — I/O supply voltage (3.3 V)
Контакт 22	I/O — User I/O pin
Контакт 23	I/O — User I/O pin
Контакт 24	I/O — User I/O pin
Контакт 25	I/O — User I/O pin
Контакт 26	I/O — User I/O pin
Контакт 27	I/O — User I/O pin
Контакт 28	I/O — User I/O pin
Контакт 29	I/O — User I/O pin
Контакт 30	I/O — User I/O pin
Контакт 31	GND — Ground
Контакт 32	I/O — User I/O pin
Контакт 33	I/O — User I/O pin
Контакт 34	I/O — User I/O pin
Контакт 35	I/O — User I/O pin
Контакт 36	I/O — User I/O pin
Контакт 37	I/O — User I/O pin
Контакт 38	I/O — User I/O pin
Контакт 39	I/O — User I/O pin
Контакт 40	I/O — User I/O pin
Контакт 41	I/O — User I/O pin
Контакт 42	VCCINT — Internal logic supply voltage (3.3 V)
Контакт 43	I/O — User I/O pin
Контакт 44	I/O — User I/O pin
Контакт 45	I/O — User I/O pin
Контакт 46	I/O — User I/O pin
Контакт 47	I/O — User I/O pin
Контакт 48	I/O — User I/O pin
Контакт 49	I/O — User I/O pin
Контакт 50	I/O — User I/O pin
Контакт 51	I/O — User I/O pin
Контакт 52	GND — Ground
Контакт 53	I/O — User I/O pin
Контакт 54	I/O — User I/O pin
Контакт 55	I/O — User I/O pin
Контакт 56	I/O — User I/O pin
Контакт 57	I/O — User I/O pin
Контакт 58	I/O — User I/O pin
Контакт 59	I/O — User I/O pin
Контакт 60	I/O — User I/O pin
Контакт 61	I/O — User I/O pin
Контакт 62	VCCIO — I/O supply voltage (3.3 V)
Контакт 63	I/O — User I/O pin
Контакт 64	I/O — User I/O pin
Контакт 65	I/O — User I/O pin
Контакт 66	I/O — User I/O pin
Контакт 67	I/O — User I/O pin
Контакт 68	I/O — User I/O pin
Контакт 69	I/O — User I/O pin
Контакт 70	I/O — User I/O pin
Контакт 71	I/O — User I/O pin
Контакт 72	GND — Ground
Контакт 73	I/O — User I/O pin
Контакт 74	I/O — User I/O pin
Контакт 75	I/O — User I/O pin
Контакт 76	I/O — User I/O pin
Контакт 77	I/O — User I/O pin
Контакт 78	I/O — User I/O pin
Контакт 79	I/O — User I/O pin
Контакт 80	I/O — User I/O pin
Контакт 81	I/O — User I/O pin
Контакт 82	VCCINT — Internal logic supply voltage (3.3 V)
Контакт 83	I/O — User I/O pin
Контакт 84	I/O — User I/O pin
Контакт 85	I/O — User I/O pin
Контакт 86	I/O — User I/O pin
Контакт 87	I/O — User I/O pin
Контакт 88	I/O — User I/O pin
Контакт 89	I/O — User I/O pin
Контакт 90	I/O — User I/O pin
Контакт 91	I/O — User I/O pin
Контакт 92	GND — Ground
Контакт 93	IN4 — Dedicated input pin 4
Контакт 94	IN3 — Dedicated input pin 3
Контакт 95	IN2 — Dedicated input pin 2
Контакт 96	IN1 — Dedicated input pin 1
Контакт 97	TDI — JTAG Test Data In
Контакт 98	TMS — JTAG Test Mode Select
Контакт 99	TCK — JTAG Test Clock
Контакт 100	TDO — JTAG Test Data Out

Типичное применение

EPM3128ATC100-5 подходит для 6 применениеs: Bus Interface Bridging and Glue Logic, Address Decoding and Chip-Select Generation, State Machines and Sequencer Implementation, Mixed-Voltage Level Translation (5 V to 3.3 V), Legacy 74-Series TTL Replacement, Industrial Control and Factory Automation.

🔧

Bus Interface Bridging and Glue Logic

The EPM3128ATC100-5 is widely used as glue logic between microprocessors, memory, and peripheral buses in industrial and embedded designs. With 128 macrocells and 80 user I/Os, the device can implement address decoders, chip-select generators, wait-state controllers, and bus mux/demux functions in a single chip. Its 5 ns pin-to-pin delay meets the timing budget for PCI, ISA, and VMEbus bridges, where deterministic timing is essential. Compared to discrete 74-series TTL parts, it consumes less board area, reduces BOM cost, and is in-system reprogrammable for late-stage design changes.

Рекомендуется

🖥️

Address Decoding and Chip-Select Generation

The MAX 3000A architecture is optimized for wide AND-OR decode trees, making the EPM3128ATC100-5 ideal for address decoding in memory-mapped systems. The 128 macrocells can implement dozens of independent chip-select signals with full address-range decoding, even across 32-bit address buses. The 5 ns tPD ensures the chip-select assertion occurs well within one memory-access cycle. Designers typically program the device once via JTAG, then store the configuration in non-volatile EEPROM that loads instantly on power-up, with no boot delay.

Рекомендуется

EPM3128ATC100-10N · Altera EPM3064ATC100-10N · Altera EPM240T100C5N · Intel

🏭

State Machines and Sequencer Implementation

Each EPM3128ATC100-5 macrocell contains a flip-flop programmable as D, T, JK, or SR with independent clock, clear, and preset controls. This makes the device excellent for implementing complex multi-state controllers such as motor-control state machines, communication protocol sequencers, and FPGA configuration controllers. With 192.3 MHz counter frequency and deterministic timing, the CPLD can drive high-bandwidth sequencing logic at full system clock rates. Designers can iterate state diagrams in MAX+PLUS II or Quartus II and reprogram in-circuit via JTAG.

Рекомендуется

EPM3128ATC100-7 · Intel EPM2210F256C5N · Intel EPM240GT100C5N · Altera

🔌

Mixed-Voltage Level Translation (5 V to 3.3 V)

The EPM3128ATC100-5 input pins accept 2.5 V, 3.3 V, and 5.0 V signals, while outputs are programmable to 2.5 V or 3.3 V. This allows the device to act as a bidirectional level translator between legacy 5 V peripherals and modern 3.3 V ASICs, microcontrollers, or FPGAs without external level-shifters. Up to 80 channels of translation can be implemented in a single device. The 5 ns propagation delay preserves timing margins in high-speed interfaces such as parallel ADC/DAC links, GPIO expansion buses, and legacy peripheral interconnects.

Рекомендуется

EPM3128ATC100-10N · Altera EPM1270T144C5N · Altera EPM3128AFC256-7N · Altera

🧩

Legacy 74-Series TTL Replacement

The EPM3128ATC100-5 can absorb the function of dozens of 74LS, 74HC, and 74FTC logic gates into a single device, dramatically reducing PCB area, power consumption, and assembly cost. With 128 macrocells, the device typically replaces 20-50 equivalent discrete SSI/MSI packages. Designers can drop in the CPLD with no changes to the board's signal routing - the same TQFP-100 footprint replaces a forest of SOIC packages. JTAG programming lets engineering teams refine logic without board respins.

Рекомендуется

EPM3064ATC100-10N · Altera EPM3032ATC44-10N · Intel EPM240T100C5N · Intel

🏭

Industrial Control and Factory Automation

With its 80 user I/Os, deterministic 5 ns timing, and proven MAX 3000A architecture, the EPM3128ATC100-5 is found in PLC digital I/O modules, motor-drive interface boards, and process-control instruments. While the commercial-temperature grade (0 °C to 70 °C) limits it to controlled environments, the pin-compatible EPM3128ATC100-10N extends operation to industrial -40 °C to +85 °C. The CPLD handles encoder decoding, PWM generation, optocoupler interface, and emergency-stop logic in a single reprogrammable device, simplifying compliance with IEC 61131-2 industrial control standards.

Рекомендуется

EPM3128ATC100-10N · Altera EPM3128ATI100-10N (Industrial-temp 100-pin TQFP variant) EPM2210GF256C5N · Intel

Сводка рекомендуемых товаров

What is the EPM3128ATC100-5?

The EPM3128ATC100-5 is an Intel (formerly Altera) MAX 3000A family CPLD with 128 macrocells, 80 user I/Os, and a 5 ns pin-to-pin propagation delay, housed in a 100-pin TQFP package. It operates from a 3.3 V supply and features EEPROM-based in-system programmability compliant with IEEE Std. 1532. According to the Altera MAX 3000A datasheet, the device targets low-cost, high-performance glue-logic and bus-interface applications.

How many logic gates and macrocells does the EPM3128ATC100-5 contain?

The EPM3128ATC100-5 contains 128 macrocells and approximately 2,500 usable gates. Each macrocell consists of a programmable AND/OR array with a configurable flip-flop that can be configured as D, T, JK, or SR. The 128 macrocells are organized into logic array blocks (LABs) interconnected by a programmable switch matrix (PIA), giving the device its deterministic timing.

What is the propagation delay of the EPM3128ATC100-5?

The EPM3128ATC100-5 has a pin-to-pin propagation delay (tPD) of 5 ns in commercial temperature and 7.5 ns per the speed-grade designation. The internal counter frequency (fCNT) is rated at 192.3 MHz. The MAX 3000A family provides deterministic timing independent of routing density, which simplifies static timing analysis compared to FPGAs.

What is the supply voltage of the EPM3128ATC100-5?

The EPM3128ATC100-5 operates from a single 3.3 V supply for both VCCINT and VCCIO. Output drivers are programmable for 2.5 V or 3.3 V logic levels, and all input pins are 2.5 V, 3.3 V, and 5.0 V tolerant, allowing the device to interface directly with mixed-voltage legacy 5 V systems without external level shifters.

Where can I download the EPM3128ATC100-5 datasheet PDF?

The EPM3128ATC100-5 datasheet is available from multiple sources, including Alldatasheet.com (document reference M595604) and Intel's archive of Altera documentation. The MAX 3000A Family datasheet covers the entire family including speed grades -4, -5, -7, and -10. Designers should use MAX+PLUS II or Quartus II software for design entry, fitting, and programming.

What is the pinout of the EPM3128ATC100-5?

The EPM3128ATC100-5 is housed in a 100-pin TQFP (Fine Line) package. Pin 1 is located at the top-left when the index mark is oriented upward, following standard JEDEC MS-026 conventions. Four dedicated input pins (IN1-IN4), 80 user I/O pins (I/O), VCCINT, VCCIO, GND, JTAG pins (TDI, TDO, TMS, TCK), and dedicated configuration/control pins (DEV_CLRn, DEV_OE, MSELn) are assigned per the MAX 3000A datasheet pin tables.

Is the EPM3128ATC100-5 still in production?

No, the EPM3128ATC100-5 is obsolete and out of production. The MAX 3000A family was discontinued by Altera (now Intel) many years ago, and remaining stock is limited to distributor inventory. Current users should plan a migration to MAX II (EPM240, EPM570) or MAX V CPLDs, which offer greater logic density, lower power, and lower cost in modern packages.

What is the best drop-in replacement for the EPM3128ATC100-5?

The best pin-to-pin drop-in replacement is the EPM3128ATC100-7, which shares the same 100-pin TQFP package, same 128 macrocells, same 80 I/Os, but a slower 7.5 ns pin-to-pin delay. For inventory that still stocks -5 speed grade, the -7 is interchangeable electrically. For new designs, the EPM3128ATC100-10N (industrial temperature) is also pin-compatible but 10 ns.

What is the difference between EPM3128ATC100-5 and EPM3128ATC100-5N?

The EPM3128ATC100-5 and EPM3128ATC100-5N are nearly identical electrically - same 128 macrocells, 80 I/Os, 5 ns tPD, and 100-pin TQFP package. The 'N' suffix indicates the lead-free / RoHS-compliant assembly version of the device, while the non-N variant uses the original SnPb or standard lead finish. Both are obsolete; choose based on the compliance requirement of the host board.

How does the EPM3128ATC100-5 compare to a Xilinx XC9500XL CPLD?

The EPM3128ATC100-5 and Xilinx XC9536XL/XC9572XL differ in macrocell count (128 vs 36-72) and process (EEPROM CMOS vs Flash CMOS), but both are 3.3 V, JTAG-programmable, and offer deterministic pin-to-pin delays. They are NOT pin-to-pin compatible - the Intel/Altera TQFP-100 footprint does not match any Xilinx device. Use Lattice ispMACH 4000 or MachXO2 for cross-brand alternatives.

What software do I use to program the EPM3128ATC100-5?

The EPM3128ATC100-5 is supported by Altera MAX+PLUS II (legacy) and Quartus II (the last Quartus version that supports MAX 3000A is Quartus II 13.0 SP1). Intel provides archived MAX+PLUS II installations for legacy design support. New designs targeting modern MAX II / MAX V devices should use Quartus Prime Lite, which does NOT support MAX 3000A.

What is the price of the EPM3128ATC100-5?

The EPM3128ATC100-5 lists at approximately USD 24.12 per unit at qty-1, dropping to USD 15.43 at qty-1000, as of 2026-09-12 from Heisener and other distributors. Because the part is obsolete and inventory is finite, prices have trended upward and lead times may extend several weeks. For new designs, MAX II/MAX V CPLDs typically cost USD 2-6 in similar volumes.

Where can I buy the EPM3128ATC100-5 online?

The EPM3128ATC100-5 can be purchased from authorized distributors including DigiKey (part number 544-1164-ND), Mouser, Heisener, Octopart, and Xecor. Stock is limited because the device is obsolete, with Heisener reporting approximately 4,640 pieces available as of 2026-09-12. For long-term supply security, consider migrating to MAX II / MAX V equivalents.

Is the EPM3128ATC100-5 RoHS compliant?

The base EPM3128ATC100-5 part number is generally non-RoHS compliant (lead-bearing finish), while the EPM3128ATC100-5N suffix variant is the lead-free RoHS-compliant version. Because the underlying silicon is identical, both versions are functionally interchangeable, but the N variant is required for any new design targeting RoHS-compliant end products. Refer to the manufacturer datasheet for the exact compliance declaration.

What is the difference between MAX 3000 and MAX 3000A?

The MAX 3000A is the enhanced revision of the MAX 3000 family, offering 2.5 V / 3.3 V output drive (vs 5 V for original MAX 3000), faster pin-to-pin delays (down to 4.5 ns vs 5 ns), and IEEE 1532 ISP compliance. The 'A' suffix in EPM3128ATC100-5 indicates MAX 3000A; older MAX 3000 devices are simply labeled EPM3128 without the 'A'. The MAX 3000A consumes less power and is pin-compatible with MAX 3000 in most packages.

Справочные инженерные данные для EPM3128ATC100-5 — сравнение, рекомендации по проектированию и информация о соответствии.

Руководство по выбору

Choose the EPM3128ATC100-5 when you need the fastest MAX 3000A speed grade (5 ns tPD) for a commercial-temperature (0-70 °C) glue-logic or bus-interface design in a 100-pin TQFP package. Choose the EPM3128ATC100-7 if 7.5 ns tPD is acceptable (and it usually is for general glue logic), since it provides identical functionality with broader inventory availability. Choose the EPM3128ATC100-5N if your end product requires RoHS compliance. Choose the EPM3128ATC100-10N for industrial -40 to +85 °C environments, accepting the slower 10 ns tPD. For new designs, migrate to MAX II (EPM240T100C5N) or MAX V CPLDs - they offer higher logic density, lower power, smaller packages, and active lifecycle support, though they require recompilation in Quartus Prime Lite. The MAX 3000A family is fully obsolete; long-term production designs should NOT depend on this part.

Сравнение с аналогами

Параметр	Этот товар	EPM3128ATC100-7	EPM3128ATC100-10N	EPM3128ATC100-10	EPM3128ATC100-10NS	EPM3128ATC100-5N
Package	TQFP-100 (Fine Line)	TQFP-100 - same	TQFP-100 - same	TQFP-100 - same	TQFP-100 - same	TQFP-100 - same
Brand	Intel (formerly Altera)	Intel - same	Intel - same	Intel - same	Intel - same	Intel - same
Macrocells	128	128 - same	128 - same	128 - same	128 - same	128 - same
Pin-to-Pin Delay (tPD)	5 ns	7.5 ns (slower)	10 ns (slower)	10 ns (slower)	10 ns (slower)	5 ns (identical)
User I/Os	80	80 - same	80 - same	80 - same	80 - same	80 - same
Usable Gates	2,500	2,500 - same	2,500 - same	2,500 - same	2,500 - same	2,500 - same
Supply Voltage	3.3 V	3.3 V - same	3.3 V - same	3.3 V - same	3.3 V - same	3.3 V - same
Operating Temperature	0 to 70 °C (Commercial)	0 to 70 °C (Commercial)	-40 to +85 °C (Industrial, N suffix = lead-free)	0 to 70 °C (Commercial)	0 to 70 °C (Commercial, NS suffix)	0 to 70 °C (Commercial, N suffix = lead-free)
Lead-Free / RoHS	No (standard lead finish)	No	Yes (N suffix)	No	Yes (NS suffix)	Yes (N suffix)
Lifecycle Status	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete	Obsolete

Ключевые отличия

Fastest MAX 3000A speed grade available (против EPM3128ATC100-7)
Identical die with lead-free / RoHS assembly (против EPM3128ATC100-5N)
Commercial temperature vs Industrial temperature grade (против EPM3128ATC100-10N)

Заметки по проектированию

Estimated: the EPM3128ATC100-5 draws approximately 35-55 mA quiescent ICC at 3.3 V on VCCINT plus additional I/O VCCIO current proportional to switching frequency and load. Decouple each VCCINT and VCCIO pin with a 0.1 µF X7R ceramic capacitor placed within 5 mm of the supply pin. Add a bulk 10 µF tantalum or low-ESR ceramic near the device. The MAX 3000A family does not require power sequencing between VCCINT and VCCIO, but simultaneous ramp-up is recommended. In standby (no switching), the device draws under 5 mA - useful for battery-backed designs.

Use a 4-layer PCB with dedicated ground and power planes for designs exceeding 50 MHz internal frequencies. Route JTAG signals (TDI, TDO, TMS, TCK) with 4-6 mil traces and keep them away from fast-switching I/O. Add 4.7 kΩ pull-ups on TMS and TDI to keep the JTAG state machine in a known state during power-up. Locate the device close to the JTAG header to minimize stub length; chained JTAG devices should share a common TCK with TDI/TDO daisy-chained. Keep I/O traces short (under 50 mm) for signals above 50 MHz to avoid reflections.

Three pitfalls are common when migrating the MAX 3000A design: (1) Quartus II dropped MAX 3000A support after v13.0 SP1 - if the original design file is unavailable, a fresh MAX+PLUS II license and legacy toolchain are required; (2) the ISP programming voltage is generated internally from VCC - external 12 V VPP is NOT required (unlike older MAX 5000/7000 devices); (3) the 'A' suffix (MAX 3000A) is NOT pin-compatible with the original MAX 3000 - the older MAX 3000 outputs were 5 V TTL, while MAX 3000A outputs are 2.5 V/3.3 V CMOS - replacing one with the other requires recompilation. Always verify the BSDL file matches the exact part number before JTAG boundary-scan testing.

Estimated: the TQFP-100 package has a typical θJA of approximately 45-55 °C/W (exact value depends on PCB copper area and airflow). With commercial 0-70 °C ambient and worst-case ICC of 150 mA, internal dissipation is roughly 0.5 W, giving a junction temperature rise of 22-28 °C above ambient - well within the 125 °C maximum. For industrial temperature variants (EPM3128ATC100-10N), ambient up to 85 °C is acceptable with similar copper area. No heatsink is required under any normal operating condition; however, the thermal performance improves dramatically with larger ground-plane copper on the top and bottom layers under the package.

Информация о соответствии

RoHS

Non Compliant

REACH

Unknown

AEC-Q100

Not Applicable

Без свинца

Без галогенов

Unknown

Конфликтные минералы

Unknown

EPM3128ATC100-5 (non-N suffix) is the standard lead-bearing variant - NOT RoHS compliant. The EPM3128ATC100-5N suffix variant is the lead-free RoHS-compliant assembly of the same silicon. REACH, halogen-free, and conflict-mineral declarations are not present in the verified web data - all marked unknown.

Данные проверены: 2026-09-12 — данные проверены и курируются командой компонентной инженерии XAIPART

Источники: Manufacturer Datasheet, Manufacturer Product Page, Distributor, Distributor, Distributor, Manufacturer Product Page, Octopart, Manufacturer Datasheet

Связанные компоненты & термины

Intel Altera EPM3128ATC100-5 MAX 3000A CPLD Complex Programmable Logic Device TQFP-100 TQFP EEPROM CMOS JTAG IEEE 1149.1 IEEE 1532 ISP in-system programmability macrocell logic array block LAB PIA programmable switch matrix 5 ns pin-to-pin delay 3.3 V supply 5 V input tolerance MAX+PLUS II Quartus II