Intel

EPM3128ATC100-5 - MAX 3000A CPLD, 128 Macrocells, 5ns TQFP-100

Référence : EPM3128ATC100-5 ✗ Fin de vie

En stock Expédié sous 1 à 3 jours ouvrés

3.3 V Vdss 100-pin TQFP (Fine Line) Package 192.3 MHz Speed EEPROM Memory

À partir de $15.43 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-12

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$24.12	$24,12
10	$21.7	$217,00
100	$19.29	$1 929,00
500	$17.36	$8 680,00
1 000	$15.43	$15 430,00

ℹ️ Tous les prix sont en USD

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EPM3128ATC100-5 Présentation

The Intel (formerly Altera) EPM3128ATC100-5 is a high-performance, low-cost CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 3000A family, delivering 128 macrocells, 80 user I/Os, and a 5 ns pin-to-pin propagation delay in a 100-pin TQFP package. The device operates from a 3.3 V supply and supports 3.3-V in-system programmability (ISP) compliant with the IEEE Std. 1532 specification, enabling concurrent ISP across multi-vendor PLD platforms.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks interconnected by a programmable switch matrix. CPLDs sit between simple SPLDs and FPGAs in the programmable logic hierarchy - they offer deterministic timing (fixed pin-to-pin delays), instant-on operation from EEPROM configuration memory, and higher logic density than discrete PAL/GAL devices while consuming less power and providing more predictable timing than most FPGAs. The MAX architecture integrates logic array blocks (LABs), an interconnect matrix, I/O control blocks, and the in-system programming engine into a single CMOS die.

Key features of the EPM3128ATC100-5 include 2,500 usable gates, 80 programmable I/O pins (each configurable as input, output, or bidirectional), four dedicated input pins, a global clear signal, and output drivers programmable for 2.5 V or 3.3 V while all inputs are 2.5 V, 3.3 V, and 5.0 V tolerant. The device supports JTAG boundary-scan testing per IEEE Std. 1149.1, has programmable security bits for design protection, and provides a typical counter frequency of 192.3 MHz. The commercial temperature grade spans 0 °C to 70 °C, and the TQFP-100 package offers a low-profile surface-mount footprint suited to high-density PCB designs.

Typical applications for the EPM3128ATC100-5 include bus interface bridging (e.g., PCI-to-ISA glue logic), address decoding and chip-select generation, state-machine and sequencer implementation, I/O expansion and level translation between 5 V and 3.3 V domains, and glue-logic replacement of discrete 74-series TTL parts. It is widely used in industrial controllers, telecom base-station control boards, and legacy design refreshes where deterministic timing, instant-on behavior, and in-field reprogrammability are required.

When designing with this device, allocate sufficient decoupling (0.1 µF per supply pin), observe the IEEE 1149.1 JTAG chain if multiple devices share the bus, and confirm Quartus II / MAX+PLUS II software support for the -5 speed grade. The 'A' suffix denotes the enhanced MAX 3000A family; the -5 suffix indicates the 7.5 ns (or 5 ns commercial) speed grade, which is the slowest of the MAX 3000A speed grades.

Alternatives de remplacement direct pour EPM3128ATC100-5 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPM3128ATC100-5 (même facteur de forme et même empreinte) — différant par Package, Operating Temperature, Propagation Delay (tPD), Usable Gates, Configuration Memory.

EPM3128ATC100-10

Altera

Package: 100-pin TQFP

Operating Temperature: 0 C to 70 C (commercial)

Propagation Delay (tPD): 10 ns