10AX090U4F45E3LG vs 10AX090U3F45E2LG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX090U4F45E3LG sa pamamagitan ng Intel at 10AX090U3F45E2LG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 10AX090U4F45E3LG | 10AX090U3F45E2LG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Manufacturer | Altera | — |
| Current Brand | Intel | — |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Family | Arria 10 GX | — |
| Logic Elements | 900000 | — |
| User I/O | 480 | — |
| Embedded Memory | 59234304 bit | — |
| Packhaging | 1932-BBGA, FCBGA | 1932-BBGA, FCBGA |
| Terminal Count | 1932 | — |
| Terminal Form | Ball | — |
| Package Code | BGA | — |
| Package Shape | Square | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| Maximum Transceiver Data Rate | [DATA_NEEDED: maximum transceiver data rate] | [DATA_NEEDED: exact Gbps] |
| DSP Block Count | [DATA_NEEDED: DSP block count] | — |
| Temperature Grade | [DATA_NEEDED: temperature grade] | — |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Speed Grade | [DATA_NEEDED: speed grade] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Series | — | Arria 10 GX |
| Logic Elements (LE) | — | 900,000 |
| Number of Logic Array Blocks (LABs) | — | [DATA_NEEDED: LAB count] |
| Embedded Memory Bits | — | 59,234,304 bits |
| Number of Transceivers | — | 48 transceiver macro channels (480 I/O references) |
| Hard Memory Controllers | — | Yes - DDR4, DDR3, QDR IV, RLDRAM 3 with hardened PHY |
| Hard PCIe Controllers | — | PCIe Gen3 x8 |
| Hard Ethernet MACs | — | 10GbE and 100GbE MACs |
| Adaptive Logic Modules (ALMs) | — | [DATA_NEEDED: ALM count] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Number of I/O Banks | — | [DATA_NEEDED: bank count] |
| Maximum User I/O Pins | — | 480 (per DigiKey listing) |
| Package Pin Pitch | — | [DATA_NEEDED: pitch] |
| Operating Temperature Grade | — | OTHER / Extended (per Partstack listing) |
| Process Technology | — | 20nm TSMC |
| Configuration Method | — | Serial (active/passive) and parallel via Quartus Prime |
| Development Tool | — | Intel Quartus Prime |