10AX115U2F45E1SG vs 10AX115U3F45E2SG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 10AX115U2F45E1SG sa pamamagitan ng Intel at 10AX115U3F45E2SG sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | 10AX115U2F45E1SG | 10AX115U3F45E2SG |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Arria 10 GX | Arria 10 GX |
| Logic Elements | 1,150,000 | — |
| Adaptive Logic Modules (ALMs) | [DATA_NEEDED: ALM count] | — |
| Embedded Memory (bits) | 68,857,600 | — |
| Embedded Memory (Mbits) | 68.86 Mbit | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | Variable-precision, hardened floating-point |
| 18x18 Multipliers | 1,518 | — |
| User I/O Pins | 480 | — |
| Transceiver Channels | 24 | — |
| Max Transceiver Data Rate | 17.4 Gbps (chip-to-chip/backplane) | — |
| Hard Memory Controllers | 6 (DDR4/DDR3/QDRII+/RLDRAM3) | 2 (DDR4/DDR3/QDRII+/RLDRAM3) |
| PCIe Hard IP | PCIe Gen3 x8 | — |
| Process Node | TSMC 20 nm | 20 nm Tri-Gate (Intel) |
| Core Voltage | 0.9 V | — |
| Packhaging | 1932-ball FCBGA, 45 x 45 mm, 1.0 mm pitch | 1932-ball FCBGA (F45, 45×45 mm, 1.0 mm pitch) |
| Grade | E1 (extended industrial, -40C to +100C) | — |
| Tindminan RoHS | Compliant | — |
| Logic Elements (LE) | — | 1,150,000 |
| Adaptive Logic Modules (ALM) | — | 427,200 |
| Embedded Memory Bits | — | 68,857,856 (≈ 52.99 Mbit) |
| Number of Transceivers | — | [DATA_NEEDED: per-die transceiver count, F45 package variant] |
| Maximum Transceiver Data Rate | — | 17.4 Gbps |
| Hard PCIe Gen3 IP Blocks | — | 2 × PCIe Gen3 (x8/x4/x2/x1) |
| Speed Grade | — | -2 (E2 commercial/extended) |
| Temperature na Operasyon | — | Industrial (junction -40 °C to +100 °C) – device grade U |
| Supply Voltage Core | — | [DATA_NEEDED: VCC/VCCP core voltage] |
| Configuration Method | — | FPGA configuration via serial/parallel flash, JTAG |
| RoHS Compliance | — | Compliant |
| Level ng MSL | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |