2ED21064S06JXUMA1 vs 2ED21084S06JXUMA1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng 2ED21064S06JXUMA1 sa pamamagitan ng Infineon at 2ED21084S06JXUMA1 sa pamamagitan ng Infineon. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Infineon
2ED21064S06JXUMA1 2ED21064S06JXUMA1 - 650V 0.7A Half-Bridge Gate Driver | Infineon

2ED21064S06JXUMA1 - 650V 0.7A Half-Bridge Gate Driver | Infineon

2ED21064S06JXUMA1 ✓ Nakahanda
Infineon
2ED21084S06JXUMA1 2ED21084S06JXUMA1 - 650V 0.7A Half-Bridge Gate Driver | Infineon

2ED21084S06JXUMA1 - 650V 0.7A Half-Bridge Gate Driver | Infineon

2ED21084S06JXUMA1 ✓ Nakahanda

Pagsanggunian na paghahambing

Parametro 2ED21064S06JXUMA1 2ED21084S06JXUMA1
Brand Infineon Infineon
Kategorya Power MOSFET Drivers Power MOSFET Drivers
Katayuan ng Lifecycle Aktibo Aktibo
Fungsi High-Side and Low-Side Gate Driver Half-bridge gate driver
Configuration Half-Bridge (2 outputs, non-inverting) —
Topolohiya High-Side, Low-Side with integrated bootstrap diode Half-bridge (high-side + low-side)
Maximum Offset / Boot Voltage 650 V —
Supply Voltage (VCC) 10 V to 20 V —
Source Current (typical) 0.29 A 0.29 A
Sink Current (typical) 0.7 A 0.7 A
Rise Time (typical) [DATA_NEEDED: rise time] —
Fall Time (typical) [DATA_NEEDED: fall time] —
Propagation Delay (typical) 100 ns —
Channel-to-Channel Delay Match [DATA_NEEDED: channel-to-channel delay match] —
Under-Voltage Lockout Yes (both channels) —
Bootstrap Diode Integrated Integrated
Input Logic Compatibility 3.3 V / 5 V CMOS —
Temperature na Operasyon -40C to +125C -40C to +125C
Packhaging PG-DSO-14 (14-pin SOIC) PG-DSO-14-49 (14-pin wide-body SOIC)
Uri ng Pagpapasok Surface Mount Surface Mount
Level ng MSL [DATA_NEEDED: MSL level] 3
Tindminan RoHS ROHS3 Compliant Compliant
Negative Gate Drive Robustness -0.7 V —
High-side Offset Voltage (max) — 650 V
VCC Supply Voltage — 10 V to 20 V
Propagation Delay Rise (typical) — 100 ns
Propagation Delay Fall (typical) — 35 ns
Input Logic — Non-inverting (HIN/LIN)
UVLO (VCC) — [DATA_NEEDED: VCC UVLO threshold]
UVLO (VBS) — [DATA_NEEDED: VBS UVLO threshold]

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