2EDN7524GXTMA1 vs 2EDN7534FXTMA1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 2EDN7524GXTMA1 sa pamamagitan ng Infineon at 2EDN7534FXTMA1 sa pamamagitan ng Infineon. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Infineon
2EDN7524GXTMA1 - 5A Dual Low-Side Gate Driver for MOSFET/GaN | Infineon
2EDN7524GXTMA1 ✓ Nakahanda
Pagsanggunian na paghahambing
| Parametro | 2EDN7524GXTMA1 | 2EDN7534FXTMA1 |
|---|---|---|
| Brand | Infineon | Infineon |
| Kategorya | Power MOSFET Drivers | Power MOSFET Drivers |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Product Type | Low-side gate driver IC | — |
| Number of Channels | 2 (dual) | — |
| Drive Current (Source/Sink) | 5 A peak | — |
| Input Logic | Non-inverting, TTL / 3.3 V CMOS-compatible | — |
| Input Voltage Tolerance | -10 V to +20 V on logic pins | — |
| Supply Voltage (VCC) | 4.5 V to 20 V [DATA_NEEDED: exact range] | — |
| Propagation Delay | 20 ns typical [DATA_NEEDED: exact figure] | — |
| Channel-to-Channel Delay Matching | 1 ns | — |
| Oras ng Pagtaas | 5 ns typical [DATA_NEEDED: exact test condition] | — |
| Time ng Pagbaba | 5 ns typical [DATA_NEEDED: exact test condition] | — |
| Output Stage | Rail-to-rail, separate source/sink | — |
| UVLO Protection | Yes | — |
| Temperature na Operasyon | -40 C to +125 C | -40C to +125C |
| Packhaging | PG-WSON-8-1 (3 mm x 3 mm) with exposed thermal pad | PG-DSO-8 |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Compliant | Compliant |
| Target Devices | Standard MOSFETs, superjunction MOSFETs, GaN HEMTs | — |
| Driver Type | — | Low-Side, Dual Channel |
| Number of Drivers | — | 2 |
| Peak Output Current | — | 5 A (source/sink) |
| Supply Voltage (VDD) | — | 4.5 V to 20 V |
| Input Voltage Range (logic pins) | — | -12 V to +22 V (absolute max) |
| Propagation Delay (typical) | — | 19 ns |
| Input Logic Compatibility | — | LV-TTL |
| Output Polarity | — | Non-Inverting |
| Output Voltage Clamping | — | Active, to VDD |
| Rise Time (typ.) | — | [DATA_NEEDED: rise time] |
| Fall Time (typ.) | — | [DATA_NEEDED: fall time] |
| Channel-to-Channel Skew | — | [DATA_NEEDED: channel skew] |
| Under-Voltage Lockout | — | Yes |
| Pin na Pinapayagan | — | Yes |