5CSEBA5U19C7SN vs 5CSEBA5U19C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA5U19C7SN sa pamamagitan ng Intel at 5CSEBA5U19C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA5U19C7SN - Cyclone V SE SoC FPGA 85K LE, ARM Cortex-A9 | Intel
5CSEBA5U19C7SN ✓ NakahandaIntel
5CSEBA5U19C7N - Cyclone V SE SoC FPGA 85K LE Dual A9 800MHz | Altera
5CSEBA5U19C7N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA5U19C7SN | 5CSEBA5U19C7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Device | 5CSEA5 | — |
| Logic Elements | 85,000 | 85,000 |
| Embedded Memory | 3.74 Mb | M10K + MLAB blocks, ~4,450 Kbits total |
| DSP 18x18 Multipliers | 224 | — |
| Hard Processor System | Single ARM Cortex-A9 MPCore with CoreSight | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | 800 MHz | 800 MHz per core |
| User I/O Pins | [DATA_NEEDED: user I/O count for U19 package] | — |
| Process Technology | 28 nm TSMC low-power | — |
| Core Voltage | 1.1 V | — |
| Packhaging | 484-pin UBG (19x19 mm) | 484-UBGA (UBGAmobile, 19x19 mm) |
| Package Code | FBGA / UBG | — |
| Operating Temperature Grade | Commercial (suffix C7) | — |
| Speed Grade | 7 | -7 (standard) |
| Tindminan RoHS | Compliant | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Temperature na Operasyon | — | 0C to +85C (commercial, junction) |
| Process Node | — | 28 nm low-power (TSMC) |
| Supply Voltage (Core) | — | 1.1 V typical |
| DSP Blocks | — | Variable-precision, 18x18 / 27x27 multipliers |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART |
| RoHS / Pb-free | — | Yes |
| Configuration Memory | — | External (active serial via HPS or FPGA) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020, reflow 260C) |
| Block Pins (User I/O) | — | Approximately 66 user I/O pins |