5CSEBA5U19I7N vs 5CSEBA5U19C8N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA5U19I7N sa pamamagitan ng Intel at 5CSEBA5U19C8N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA5U19I7N - Cyclone V SE SoC FPGA 85K LE Dual ARM Cortex-A9 | Intel
5CSEBA5U19I7N ✓ NakahandaIntel
5CSEBA5U19C8N - Cyclone V SE SoC FPGA, 85K LE, Dual ARM Cortex-A9 | Intel
5CSEBA5U19C8N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA5U19I7N | 5CSEBA5U19C8N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Product Type | SoC FPGA (System-on-Chip FPGA) | — |
| Series | Cyclone V SE | — |
| Logic Elements | 85,000 | 85,000 LE |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| Core Frequency | 800 MHz (typical), up to 925 MHz | — |
| Process Technology | 28 nm TSMC low-power | 28 nm TSMC |
| Packhaging | 484-pin UBG (UFBGA) 19x19 mm | 484-UBGA (U19, 19x19 mm) |
| Volte ng Pagbibigay | 1.1 V core | — |
| FPGA User I/O | 66 (per datasheet front-page snippet) | — |
| Embedded Memory | Approximately 4,450 Kbits | 3.88 Mbit |
| DSP Blocks | 87 variable-precision (18x18 multipliers) | — |
| Transceivers | Up to 5 Gbps (Cyclone V SE feature) | — |
| HPS Peripherals | USB 2.0 OTG, EMAC, CAN, SPI, I2C, UART, SD/MMC, NAND | — |
| Temperature na Operasyon | -40C to +100C (Industrial grade, suffix I) | 0C to +85C (commercial) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (SMD/SMT) |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Compliant (per Heisener listing and product family) | Compliant |
| Family | — | Cyclone V SE (SoC FPGA) |
| Adaptive Logic Modules (ALMs) | — | 32,070 ALM |
| Processor Cores | — | Dual ARM Cortex-A9 MPCore |
| Core Maximum Frequency | — | 925 MHz (datasheet); 600 MHz commercial speed grade |
| L1 Cache (Instruction) | — | 2 x 32 kB |
| L1 Cache (Data) | — | 2 x 32 kB |
| L2 Cache | — | 512 kB shared |
| FPGA User I/Os | — | 66 I/O |
| Core Voltage | — | 1.1 V |
| Ball Pitch | — | [DATA_NEEDED: ball pitch in mm] |
| Speed Grade | — | C8 (0.85 ns, commercial) |