5CSEBA6U19A7N vs 5CSEBA5U19C7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA6U19A7N sa pamamagitan ng Intel at 5CSEBA5U19C7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA5U19C7N - Cyclone V SE SoC FPGA 85K LE Dual A9 800MHz | Altera
5CSEBA5U19C7N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA6U19A7N | 5CSEBA5U19C7N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | Cyclone V SE SoC FPGA | Cyclone V SE SoC FPGA |
| Device Variant | 5CSEA6 (U19) | — |
| Logic Elements | 110,000 | 85,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Clock Frequency | 700 MHz | — |
| Core Voltage | 1.1 V | — |
| Packhaging | 484-pin UBGFA / UFBGA (19x19 mm) | 484-UBGA (UBGAmobile, 19x19 mm) |
| Operating Temperature Grade | Automotive AEC-Q100 | — |
| Supply Form | Tray | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| FPGA Architecture | SRAM-based, low-power process | — |
| Memory Blocks | M10K + MLAB embedded memory | — |
| DSP Blocks | Variable-precision DSP | Variable-precision, 18x18 / 27x27 multipliers |
| Peripherals | EMAC, USB, CAN, SPI, I2C, UART, NAND/NOR flash, DDR3 controller with ECC | — |
| Tindminan RoHS | Compliant | — |
| HPS Maximum Frequency | — | 800 MHz per core |
| Temperature na Operasyon | — | 0C to +85C (commercial, junction) |
| Speed Grade | — | -7 (standard) |
| Process Node | — | 28 nm low-power (TSMC) |
| Supply Voltage (Core) | — | 1.1 V typical |
| Embedded Memory | — | M10K + MLAB blocks, ~4,450 Kbits total |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART |
| RoHS / Pb-free | — | Yes |
| Configuration Memory | — | External (active serial via HPS or FPGA) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020, reflow 260C) |
| Block Pins (User I/O) | — | Approximately 66 user I/O pins |