5CSEBA6U19C6N vs 5CSEBA2U19C6N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5CSEBA6U19C6N sa pamamagitan ng Altera at 5CSEBA2U19C6N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
5CSEBA2U19C6N - Cyclone V SE SoC FPGA, 25K LE, ARM Cortex-A9 | Intel
5CSEBA2U19C6N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5CSEBA6U19C6N | 5CSEBA2U19C6N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Manufacturer | Altera (Intel) | — |
| Series | Cyclone V SE SoC FPGA | — |
| Device Variant | 5CSEA6 (U19 package) | — |
| Logic Elements | 110K | 25 K |
| HPS Architecture | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Frequency | 925 MHz | — |
| FPGA Speed Grade | -6 (industrial) | — |
| Packhaging | 484-UBGA (UBGА, 19x19 mm) | 484-pin UBGA (19x19 mm) |
| Bilang ng Pin | 484 | — |
| Process Technology | TSMC 28 nm low-power | TSMC 28 nm low-power |
| User I/O | 66 (per Heisener) / configurable LVDS/LVCMOS | — |
| Hard IP Blocks | PCIe Gen2, multi-port memory controller, ARM Cortex-A9 HPS | — |
| DSP Blocks | Variable-precision DSP | Variable-precision DSP |
| Memory | Embedded M10K blocks | — |
| Temperature na Operasyon | -40C to +100C (industrial) | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Tindminan RoHS | Compliant (per Altera/Intel product page) | Compliant |
| Level ng MSL | 3 (per BGA package) | — |
| Family | — | Cyclone V SE SoC FPGA |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Clock Frequency | — | 925 MHz |
| Operating Temperature Grade | — | Commercial (other) |
| Memory Interfaces | — | DDR2, DDR3, LPDDR2 with ECC |
| HPS Peripherals | — | GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC |
| L2 Cache | — | 512 KB shared |
| L1 Cache per Core | — | 32 KB I-cache + 32 KB D-cache |
| FPGA-to-HPS Bridges | — | AXI-32/AXI-64, FPGA-to-SDRAM ports |