5CSEBA6U19C6N vs 5CSEBA2U19C6N 比較

詳細並排比較 5CSEBA6U19C6N 由 Altera 與 5CSEBA2U19C6N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 5CSEBA6U19C6N 5CSEBA2U19C6N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 啟用中
Manufacturer Altera (Intel) —
Series Cyclone V SE SoC FPGA —
Device Variant 5CSEA6 (U19 package) —
Logic Elements 110K 25 K
HPS Architecture Dual ARM Cortex-A9 MPCore with CoreSight —
HPS Frequency 925 MHz —
FPGA Speed Grade -6 (industrial) —
封裝 484-UBGA (UBGА, 19x19 mm) 484-pin UBGA (19x19 mm)
腳位數 484 —
Process Technology TSMC 28 nm low-power TSMC 28 nm low-power
User I/O 66 (per Heisener) / configurable LVDS/LVCMOS —
Hard IP Blocks PCIe Gen2, multi-port memory controller, ARM Cortex-A9 HPS —
DSP Blocks Variable-precision DSP Variable-precision DSP
Memory Embedded M10K blocks —
工作溫度 -40C to +100C (industrial) —
安裝類型 Surface Mount (BGA) Surface Mount
RoHS 狀態 Compliant (per Altera/Intel product page) Compliant
MSL 等級 3 (per BGA package) —
Family — Cyclone V SE SoC FPGA
Hard Processor System — Dual ARM Cortex-A9 MPCore with CoreSight
HPS Maximum Clock Frequency — 925 MHz
Operating Temperature Grade — Commercial (other)
Memory Interfaces — DDR2, DDR3, LPDDR2 with ECC
HPS Peripherals — GbE, USB 2.0 OTG, SATA, CAN, UART, SPI, I2C, SD/SDIO/MMC
L2 Cache — 512 KB shared
L1 Cache per Core — 32 KB I-cache + 32 KB D-cache
FPGA-to-HPS Bridges — AXI-32/AXI-64, FPGA-to-SDRAM ports

資料表與資源

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