5M240ZT100I5N vs 5M240ZT100C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M240ZT100I5N sa pamamagitan ng Altera at 5M240ZT100C5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
5M240ZT100C5N - 240 Logic Element MAX V CPLD, 100TQFP | Intel / Altera
5M240ZT100C5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5M240ZT100I5N | 5M240ZT100C5N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX V | MAX V |
| Series | 5M240Z | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements | 240 | — |
| Macrocells | 192 | 192 |
| User Flash Memory | 8 Kbit | 8 Kbits |
| Maximum User I/O | 114 | — |
| User I/O Pins (per datasheet) | 79 | — |
| Bilang ng Pins | 100 | — |
| Package Type | TQFP-100 (T100) | — |
| Package Body Size | 14 x 14 mm | — |
| Lead Pitch | 0.50 mm | — |
| Core Voltage (VCCINT) | 1.8 V | — |
| I/O Bank Voltage (VCCIO) | 1.2 V to 3.3 V (bank-dependent) | — |
| Speed Grade | -5 | — |
| Maximum Internal Frequency | 118.3 MHz | 118.3 MHz |
| Pin-to-Pin Delay (tPD1) | 7.5 ns (per datasheet header) | — |
| Temperature na Operasyon | -40 C to +100 C (Industrial) | 0C to +85C (commercial grade) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) |
| Configuration Memory | Non-volatile flash (instant-on) | Internal flash (non-volatile, instant-on) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead-Free / RoHS | Yes (LEAD FREE per datasheet header) | — |
| Level ng MSL | [DATA_NEEDED: MSL Level] | [DATA_NEEDED: MSL level] |
| AEC-Q100 Automotive | Not qualified (Industrial grade) | — |
| Logic Elements (LEs) | — | 240 |
| User I/Os | — | 79 |
| Pin-to-Pin Logic Delay (Tpd1) | — | 7.5 ns (per distributor classification) |
| Operating Voltage (VCCINT) | — | 3.3 V (internal 1.8 V core derived) |
| I/O Bank Voltages Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| Packhaging | — | TQFP-100 (14 x 14 mm, 0.5 mm pitch) |
| Tindminan RoHS | — | Compliant (per LCSC listing) |