5M570ZE64I5N vs 5M1270ZT144C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng 5M570ZE64I5N sa pamamagitan ng Intel at 5M1270ZT144C5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
5M1270ZT144C5N - MAX V CPLD 980 Macrocells 114 I/O TQFP-144 | Intel / Altera
5M1270ZT144C5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | 5M570ZE64I5N | 5M1270ZT144C5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX V | MAX V |
| Programmable Type | In System Programmable | — |
| Number of Logic Elements / Blocks | 570 | — |
| Number of Macrocells | 440 | — |
| Number of User I/O | 54 | — |
| Propagation Delay tpd(1) Max | 9 ns | — |
| Internal Supply Voltage VCCINT | 1.71 V to 1.89 V (1.8 V typical) | — |
| Hanay ng Temperature na Operasyon | -40 C to +100 C (TJ) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Packhaging / Kaso | 64-TQFP Exposed Pad (EQFP-64) | — |
| Supplier Device Package | 64-EQFP (7x7 mm) | — |
| Configuration Memory | Non-volatile Flash | Flash (non-volatile, in-system programmable) |
| Programmable I/O Voltage Standards | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt I/O) | — |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG in-system programmable (Altera Quartus II) |
| Tindminan RoHS | Compliant | Compliant |
| Lead-Free | Yes | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements | — | 1270 |
| Macrocells | — | 980 |
| User I/Os | — | 114 |
| Maximum Internal Frequency | — | 118.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 6.2 ns |
| Internal Frequency (typical) | — | 201 MHz |
| User Flash Memory (UFM) | — | 8 Kbits |
| VCCINT (Core Supply) | — | 1.71 V to 1.89 V |
| VCCIO (I/O Supply, per bank) | — | 1.2 V to 3.3 V |
| Number of I/O Banks | — | 4 |
| Supported I/O Standards | — | LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins |
| JTAG Interface | — | IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1) |
| Program/Erase Cycles | — | Up to 100,000 |
| Packhaging | — | TQFP-144 (22 x 22 mm, 0.5 mm pitch) |
| Temperature na Operasyon | — | 0 C to +85 C (commercial grade) |