A3PE3000-FGG324 vs A3PE3000-FG324 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng A3PE3000-FGG324 sa pamamagitan ng Microchip Technology at A3PE3000-FG324 sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
A3PE3000-FGG324 - ProASIC3E FPGA 3M Gates 221 I/O | Microchip
A3PE3000-FGG324 ✓ NakahandaMicrochip Technology
A3PE3000-FG324 - ProASIC3E FPGA 3M Gates 324-BGA | Microchip
A3PE3000-FG324 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | A3PE3000-FGG324 | A3PE3000-FG324 |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | ProASIC3E | ProASIC3E Flash Family |
| System Gates | 3000000 gates | 3,000,000 |
| Logic Cells | 75264 cells | — |
| Number of I/O | 221 | — |
| Core Supply Voltage | 1.425 V to 1.575 V | 1.5 V |
| Process Technology | 130 nm flash | 130 nm CMOS |
| Maximum System Frequency | 231 MHz | 231 MHz |
| Embedded Flash Bits | 516096 bits | — |
| Configuration Type | Flash (nonvolatile, single-chip) | — |
| Packhaging | 324-Ball FBGA (FGG324) | 324-ball FBGA (FG324), 19 x 19 mm, 1.63 mm height, 1.0 mm pitch |
| Package Dimensions | 19 x 19 mm, 1.63 mm height, 1 mm pitch | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Soft ARM Support | Yes (optional soft ARM core support) | — |
| Tindminan RoHS | Green (compliant) | RoHS Non-Compliant (contains lead, per digichip listing) |
| Temperature na Operasyon | [DATA_NEEDED: Operating Temperature] | [DATA_NEEDED: operating temperature range] |
| Technology Node Family | CMOS flash FPGA | — |
| Logic Elements / CLBs | — | 75,264 |
| User I/Os | — | 221 |
| Configuration Technology | — | Flash (non-volatile, single-chip) |
| In-System Programming | — | Yes (JTAG, IEEE 1532-compliant) |
| Security | — | 128-bit AES decryption via JTAG; FlashLock |
| Packaging | — | Tray |
| Embedded Memory | — | [DATA_NEEDED: embedded SRAM bits] |
| PLLs | — | [DATA_NEEDED: number of PLLs] |
| I/O Standards Supported | — | [DATA_NEEDED: supported I/O standards] |
| Lead Free Status | — | Contains Lead (per digichip listing) |
| Device ESD/HBM Rating | — | [DATA_NEEDED: ESD rating] |