A42MX24-2PLG84I vs A42MX09-2PLG84I Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng A42MX24-2PLG84I sa pamamagitan ng Microchip Technology at A42MX09-2PLG84I sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
A42MX24-2PLG84I - 36K Gate Antifuse FPGA, 84-PLCC | Microchip
A42MX24-2PLG84I ✓ NakahandaMicrochip Technology
A42MX09-2PLG84I - 14K Gate 5V FPGA 84-PLCC | Microchip
A42MX09-2PLG84I ✓ NakahandaPagsanggunian na paghahambing
| Parametro | A42MX24-2PLG84I | A42MX09-2PLG84I |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MX (42MX) | MX (42MX) |
| System Gates | 36000 gates | 14000 |
| Logic Cells | 912 cells | 336 |
| User I/O | 72 | — |
| Technology | 0.45 um antifuse | — |
| Core Architecture Voltage | 5.0 V | — |
| I/O Voltage Support | 3.3 V / 5.0 V mixed | — |
| Speed Grade | -2 | -2 |
| Programmability | One-Time Programmable (antifuse) | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| Packhaging | 84-PLCC (J-Lead) | 84-PLCC (J-Lead), surface mount |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration | No external boot device required | — |
| Dedicated Decode Blocks | D-modules (wide-input AND, CPLD-like) | — |
| Tindminan RoHS | Lead Free (per Kynix listing) | Lead Free |
| Packaging | Tray | — |
| Primary Applications | ASIC alternative, legacy PLD integration | — |
| User I/O Pins | — | 72 |
| Core Supply Voltage | — | 4.5 V to 5.5 V |
| I/O Supply Voltage | — | 3 V to 3.6 V (dual supply) |
| Clock-to-Out | — | 5.6 ns |
| Dual-Port SRAM Access Time | — | 5 ns |
| Dual-Port SRAM | — | Up to 2.5 kbits configurable |
| Maximum Performance | — | 250 MHz |
| Process Technology | — | 0.45 um |
| Number of Logic Blocks | — | [DATA_NEEDED: number of logic blocks] |