AD7715ACHIPS-5 vs AD7715ACHIPS-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng AD7715ACHIPS-5 sa pamamagitan ng Analog Devices at AD7715ACHIPS-3 sa pamamagitan ng Analog Devices. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Analog Devices
AD7715ACHIPS-5 - 16-Bit Sigma-Delta ADC, 3V/5V, 450uA | Analog Devices
AD7715ACHIPS-5 NrndPagsanggunian na paghahambing
| Parametro | AD7715ACHIPS-5 | AD7715ACHIPS-3 |
|---|---|---|
| Brand | Analog Devices | Analog Devices |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | NRND | Aktibo |
| Architecture | 16-bit sigma-delta ADC | — |
| Pangangasiwaan | 16 bits, no missing codes | 16 bits |
| Number of Input Channels | 1 differential / pseudo-differential | — |
| Volte ng Pagbibigay | 3 V or 5 V nominal | 3 V nominal (3 V variant; -5 variant operates at 5 V) |
| Total Supply Current | 450 uA typical at 3 V supply | — |
| Master Clock Frequency | Up to 5 MHz at 5 V, up to 2.4576 MHz at 3 V | — |
| On-chip PGA | Yes, programmable gain (1 to 128) | — |
| Input Range | 20 mV to 2.5 V (gain-dependent, 5 V supply) | — |
| Output Data Rate | Programmable via digital filter first-notch (typ. 10 Hz to 1 kHz) | — |
| Calibration | Self-calibration and system-calibration modes | On-chip self-calibration (zero-scale, full-scale) |
| Serial Interface | SPI, QSPI, MICROWIRE, DSP-compatible 3-wire serial | 3-wire SPI/QSPI/MICROWIRE compatible |
| Packhaging | Bare die (CHIPS) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Tindminan RoHS | Compliant (per Analog Devices product page) | [DATA_NEEDED: RoHS status for die form] |
| Lead-Free | Yes (bare-die construction - consult factory) | — |
| Number of Inputs | — | 1 differential |
| ADC Architecture | — | Sigma-Delta (charge balancing) |
| Kuru-kuryente ng Pagbibigay | — | 450 uA max at 3 V / 1 MHz MCLK |
| Master Clock Range | — | 1 MHz typical (see datasheet) |
| Integral Nonlinearity (INL) | — | 0.0015% |
| Missing Codes | — | None (16 bits guaranteed) |
| Programmable Gains | — | 1, 2, 32, 128 |
| Input Type | — | Differential analog input pair |
| Package Type | — | Bare die / CHIPS |
| Terminal Count | — | 16 (die pads) |