ADC32J44IRGZ25 vs ADS62P48IRGC25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng ADC32J44IRGZ25 sa pamamagitan ng Texas Instruments at ADS62P48IRGC25 sa pamamagitan ng Texas Instruments. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Texas Instruments
ADC32J44IRGZ25 - Dual 14-Bit 125MSPS ADC w/ JESD204B | TI
ADC32J44IRGZ25 ✓ NakahandaTexas Instruments
ADS62P48IRGC25 - Dual 14-Bit 210MSPS ADC | Texas Instruments
ADS62P48IRGC25 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | ADC32J44IRGZ25 | ADS62P48IRGC25 |
|---|---|---|
| Brand | Texas Instruments | Texas Instruments |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Manufacturer | Texas Instruments | — |
| Series | ADC32J4x | — |
| Number of Channels | 2 | 2 (Dual) |
| Pangangasiwaan | 14 bit | 14 bit |
| Sampling Rate (max) | 125 MSPS | — |
| Architecture | Pipelined | Pipelined |
| Input Type | Differential | Differential analog inputs |
| Data Interface | JESD204B | — |
| Number of Lanes | Up to 2 | — |
| Max Lane Rate | 3.125 Gbps | — |
| Supply Voltage (Analog) | 1.8 V | — |
| Supply Voltage (Digital) | 1.8 V | — |
| Power Consumption | 227 mW/Ch at 160 MSPS | — |
| SNR | 72.2 dBFS at fIN = 70 MHz | — |
| SFDR | 87 dBc at fIN = 70 MHz | — |
| Channel Isolation | 105 dB | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | — |
| Packhaging | 48-VQFN (7x7 mm) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant | Compliant |
| Sample Rate (max) | — | 210 MSPS |
| Output Interface | — | DDR LVDS / Parallel CMOS (selectable) |
| Analog Supply Voltage | — | 1.8 V |
| Digital Supply Voltage | — | 3.3 V |
| Hanay ng Temperature na Operasyon | — | -40 C to +85 C (Industrial) |
| Packhaging / Kaso | — | 64-VQFN (RGC) 9x9 mm (HVQCCN) |
| Bilang ng Pin | — | 64 |
| Level ng MSL | — | 3 |
| Lead Free | — | Yes |
| Input Clock Type | — | LVDS differential clock |
| Internal Dither | — | Yes (programmable) |
| Programmable Gain | — | Yes (improves SFDR at lower FS inputs) |