ATSAMA5D42A-CUR vs ATSAMA5D42A-CU Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng ATSAMA5D42A-CUR sa pamamagitan ng Microchip Technology at ATSAMA5D42A-CU sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
ATSAMA5D42A-CUR - 600MHz ARM Cortex-A5 MPU, 361-TFBGA | Microchip
ATSAMA5D42A-CUR ✓ NakahandaMicrochip Technology
ATSAMA5D42A-CU - ARM Cortex-A5 MPU 600MHz 361-TFBGA | Microchip
ATSAMA5D42A-CU ✓ NakahandaPagsanggunian na paghahambing
| Parametro | ATSAMA5D42A-CUR | ATSAMA5D42A-CU |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | Microcontrollers | Microcontrollers |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Core Architecture | ARM Cortex-A5 (32-bit, single core) | ARMv7-A with Thumb-2, NEON, FPU, MMU |
| Maximum CPU Clock | 600 MHz | — |
| SIMD Engine | ARM NEON | — |
| Floating Point Unit | Yes (single and double precision) | — |
| L1 Cache | 32 KB I-cache + 32 KB D-cache (per core) | — |
| L2 Cache | 128 KB | 128 KByte |
| Internal ROM | 128 KB | — |
| Internal SRAM | 128 KB | 128 KByte |
| External Memory Support | LPDDR, LPDDR2, DDR2 | — |
| Packhaging | 361-TFBGA (16 x 16 mm) | 361-TFBGA (16x16 mm, 0.8 mm pitch) |
| ADC | 5-channel, 10-bit with resistive touchscreen controller | — |
| Crypto Acceleration | AES, SHA-256, TRNG (hardware) | — |
| Memory Integrity Monitor | ICM based on SHA-256 (secure boot) | — |
| USB | USB 2.0 High-Speed Host and Device | — |
| Networking | 10/100 Mbps EMAC with MII/RMII | — |
| Temperature na Operasyon | -40 C to +85 C (industrial) | -40C to +85C (industrial) |
| Supply Voltage (Core) | [DATA_NEEDED: VDDCORE nominal] | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Core Processor | — | ARM Cortex-A5 |
| Number of Cores | — | 1 |
| Width ng Data Bus | — | 32-bit |
| Maximum Clock Speed | — | 600 MHz |
| L1 Instruction Cache | — | 32 KByte |
| L1 Data Cache | — | 32 KByte |
| Operating Voltage (Core) | — | 1.2 V to 1.32 V |
| Operating Voltage (I/O) | — | 1.8 V / 3.3 V |
| DDR Memory Controller | — | DDR2/LPDDR/DDR3, 16-bit data bus |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |
| Tindminan RoHS | — | Compliant |