CDK1308CILP40 vs CDK1308AILP40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng CDK1308CILP40 sa pamamagitan ng MaxLinear at CDK1308AILP40 sa pamamagitan ng MaxLinear. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | CDK1308CILP40 | CDK1308AILP40 |
|---|---|---|
| Brand | MaxLinear | MaxLinear |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Pangangasiwaan | 10 bit | 10 bit |
| Sampling Rate (max) | 40 MSPS | — |
| Family Sampling Rates | 20 / 40 / 65 / 80 MSPS | — |
| Architecture | Pipeline | Proprietary, digital error correction |
| Number of Channels | 1 | — |
| Analog Supply Voltage | 1.8 V | — |
| Digital I/O Supply Voltage | 1.7 V to 3.6 V | — |
| Power Dissipation (65 MSPS) | 38 mW | — |
| SNR | 61.6 dB at Fin = 8 MHz | — |
| Input Type | Single-ended / Differential | — |
| Reference Type | Internal | — |
| Output Interface | Parallel CMOS | — |
| Packhaging | LQFP-40 | 40-pin QFN |
| Temperature na Operasyon | -40 C to +85 C | — |
| Tindminan RoHS | Compliant | Compliant (per distributor listings) |
| Pin Compatible With | CDK1307 family | — |
| Maximum Sample Rate | — | 20 MSPS |
| Family Sample Rate Options | — | 20 / 40 / 65 / 80 MSPS |
| Reference | — | Internal (no external reference required) |
| Digital Interface | — | CMOS, parallel |
| Control Interface | — | CMOS |
| Power-Down Pin (PD_N) | — | Yes (active low) |
| Sleep Pin (SLP_N) | — | Yes (active low) |
| Uri ng Pagpapasok | — | Surface Mount |
| Power Consumption | — | Ultra-low (per family datasheet, exact value [DATA_NEEDED: power consumption mW]) |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Volte ng Pagbibigay | — | [DATA_NEEDED: AVDD / DRVDD values] |
| Manufacturer | — | MaxLinear (formerly Exar Corporation) |