EP1810GI-45 vs EP1810GC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GI-45 sa pamamagitan ng Altera at EP1810GC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810GI-45 | EP1810GC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 16 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Speed Grade | -45 | — |
| Technology | CMOS | CMOS, UV-erasable EPROM cells |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| Bilang ng Pin | 68 | — |
| Uri ng Pagpapasok | Through-Hole | Through Hole |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| Tindminan RoHS | Non-compliant (ceramic PGA) | Not applicable (legacy ceramic package) |
| Lead-Free | No | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | [DATA_NEEDED: VCC range] |
| Logic Family | — | Altera Classic EPLD |
| Packhaging | — | CPGA-68 (Ceramic Pin Grid Array, 68-pin) |
| Bilang ng Pins | — | 68 |
| Propagation Delay (tpd max) | — | 40 ns |
| Maximum Inputs | — | 64 |
| Maximum Outputs | — | 48 |
| I/O Standard | — | TTL-compatible |
| Programming Method | — | UV erasure + EPROM programming |
| Lead-Free Status | — | Not applicable |
| Manufacturer (current source) | — | Rochester Electronics (authorized Altera EPLD partner) |
| Original Manufacturer | — | Altera Corporation (now Intel FPGA) |