EP1810GI-45 vs EP1810JC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GI-45 sa pamamagitan ng Altera at EP1810JC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810GI-45 | EP1810JC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | Altera/Intel Classic EPLD (EP1810 series) |
| Macrocells | 24 | 48 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Speed Grade | -45 | — |
| Technology | CMOS | CMOS, UV-erasable (windowed ceramic DIP) |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| Bilang ng Pin | 68 | — |
| Uri ng Pagpapasok | Through-Hole | Through-hole |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| Tindminan RoHS | Non-compliant (ceramic PGA) | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | No | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -40 °C to 85 °C (industrial, per distributor listings) |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Packhaging | — | 28-pin ceramic DIP (J) with quartz window |
| Erasure Method | — | UV light (windowed package) |
| Katayuan ng Lifecycle | — | NRND (Not Recommended for New Designs) |