EP1810GI-45 vs EP1810JC-25 比較
詳細並排比較 EP1810GI-45 由 Altera 與 EP1810JC-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GI-45 | EP1810JC-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | Altera/Intel Classic EPLD (EP1810 series) |
| Macrocells | 24 | 48 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Speed Grade | -45 | — |
| Technology | CMOS | CMOS, UV-erasable (windowed ceramic DIP) |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| 腳位數 | 68 | — |
| 安裝類型 | Through-Hole | Through-hole |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| RoHS 狀態 | Non-compliant (ceramic PGA) | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | No | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -40 °C to 85 °C (industrial, per distributor listings) |
| 供應電壓 | [DATA_NEEDED: VCC range] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: max fMAX] |
| Input Lines | — | 60 (including I/O) |
| I/O Lines | — | 48 |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| 封裝 | — | 28-pin ceramic DIP (J) with quartz window |
| Erasure Method | — | UV light (windowed package) |
| 生命週期狀態 | — | NRND (Not Recommended for New Designs) |