EP1810GI-45 vs EP1810JM-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810GI-45 sa pamamagitan ng Altera at EP1810JM-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810GI-45 | EP1810JM-45 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | 48 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | 45 ns (max, -45 speed grade) |
| Speed Grade | -45 | — |
| Technology | CMOS | CMOS, UV-EPROM configuration |
| Package Type | Ceramic Pin Grid Array with UV window | JLCC-68 (ceramic J-leaded chip carrier) |
| Bilang ng Pin | 68 | 68 |
| Uri ng Pagpapasok | Through-Hole | Surface Mount (J-lead) |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| Tindminan RoHS | Non-compliant (ceramic PGA) | [DATA_NEEDED: RoHS status - legacy mil-spec part] |
| Lead-Free | No | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -55 C to +125 C (military grade) |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | — |
| Device Family | — | Classic EPLD (EP1810 series) |
| Usable Gates | — | ~900 gates |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Package Code | — | JM (windowed ceramic, UV-erasable) |
| I/O Compatibility | — | CMOS / TTL |
| Configuration Method | — | JEDEC fuse map, EPROM programmer |
| Programming Technology | — | UV-erasable EPROM (non-volatile, instant-on) |
| Logic Type | — | EPLD / PLD (programmable logic device) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |