EP1810JI-35 vs EP1810LI-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-35 sa pamamagitan ng Intel at EP1810LI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810JI-35 EP1810LI-35
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family Classic EPLD —
Macrocells 48 48
Logic Array Blocks 8 LABs of 16 macrocells —
Dedicated Inputs 48 —
Pin-to-Pin Propagation Delay (tPD) 35 ns —
Speed Grade -35 35 (slowest in EP1810L family)
Packhaging 28-pin JLCC (J-leaded ceramic, windowed) 68-pin PLCC (J-Lead, plastic)
Process Technology CMOS EPROM (UV-erasable) —
Temperature na Operasyon -40C to +85C (Industrial) -40 C to +85 C (industrial, 'I' suffix)
Volte ng Pagbibigay 5 V (typical classic EPLD) 5 V (TTL-compatible I/O)
Programmability UV-erase, windowed for lab reprogram —
Uri ng Pagpapasok Through-Hole (J-lead) Surface Mount (PLCC socket compatible)
Tindminan RoHS [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] [DATA_NEEDED: RoHS compliance status]
Level ng MSL [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL rating]
Programming Interface JEDEC fuse file via legacy programmer —
Manufacturer — Rochester Electronics, LLC (original Altera design)
Part Family — Altera Classic EPLD
Device Type — Erasable Programmable Logic Device (EPLD)
Propagation Delay (tPD) — 35 ns
Pin/Package Code — PLCC-68 / PQCC68
Technology — CMOS, UV-erasable EPROM configuration cell
JTAG Boundary Scan — IEEE 1149.1 compliant
Logic Elements — Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA)
Lead-Free — [DATA_NEEDED: lead-free status]

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