EP1810JI-35 vs EP1810LI-35 比較
詳細並排比較 EP1810JI-35 由 Intel 與 EP1810LI-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JI-35 | EP1810LI-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Classic EPLD | — |
| Macrocells | 48 | 48 |
| Logic Array Blocks | 8 LABs of 16 macrocells | — |
| Dedicated Inputs | 48 | — |
| Pin-to-Pin Propagation Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | 35 (slowest in EP1810L family) |
| 封裝 | 28-pin JLCC (J-leaded ceramic, windowed) | 68-pin PLCC (J-Lead, plastic) |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| 工作溫度 | -40C to +85C (Industrial) | -40 C to +85 C (industrial, 'I' suffix) |
| 供應電壓 | 5 V (typical classic EPLD) | 5 V (TTL-compatible I/O) |
| Programmability | UV-erase, windowed for lab reprogram | — |
| 安裝類型 | Through-Hole (J-lead) | Surface Mount (PLCC socket compatible) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] | [DATA_NEEDED: RoHS compliance status] |
| MSL 等級 | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Programming Interface | JEDEC fuse file via legacy programmer | — |
| Manufacturer | — | Rochester Electronics, LLC (original Altera design) |
| Part Family | — | Altera Classic EPLD |
| Device Type | — | Erasable Programmable Logic Device (EPLD) |
| Propagation Delay (tPD) | — | 35 ns |
| Pin/Package Code | — | PLCC-68 / PQCC68 |
| Technology | — | CMOS, UV-erasable EPROM configuration cell |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Logic Elements | — | Logic Array Blocks (LABs) connected via Programmable Interconnect Array (PIA) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |