EP1810JI-45 vs EP1810GM883B Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-45 sa pamamagitan ng Altera at EP1810GM883B sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810JI-45 | EP1810GM883B |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Manufacturer | Altera (now Intel FPGA) | — |
| Series | Classic EPLD Family | — |
| Device Type | UV-Erasable / OTP Complex PLD | — |
| Macrocell Count | 48 | — |
| Maximum Operating Frequency | 33.3 MHz | — |
| Propagation Delay (tPD) | 50 ns | 50 ns max |
| Configurable I/O Lines | 48 | — |
| Dedicated Inputs | 12 | 12 |
| Technology | CMOS EPROM | CMOS, UV-erasable |
| Package Code | QCCJ | — |
| Package Type | 68-pin JLCC (J-leaded ceramic chip carrier) | Ceramic Pin Grid Array (PGA), 84 pins |
| Terminal Form | J BEND | — |
| Package Shape | SQUARE | — |
| Number of Terminals | 68 | — |
| Temperature Grade | INDUSTRIAL | — |
| Temperature na Operasyon | -40 °C to +85 °C | -55 °C to +125 °C (Military, MIL-STD-883B) |
| Volte ng Pagbibigay | 5 V (TTL compatible) | — |
| Programming Method | UV-erase (windowed) / OTP via JEDEC | UV-erasable / Altera programming hardware |
| Device Family | — | EP1810 (Classic EPLD) |
| Macrocells | — | 48 |
| User Flip-Flops | — | Up to 64 |
| Total Inputs | — | 60 |
| I/O Pins | — | 48 (bidirectional, tri-state) |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| Package Designator | — | GM (ceramic PGA) |
| Processing Level | — | MIL-STD-883B (Class B) |
| Uri ng Pagpapasok | — | Through-hole (PGA socket or PCB through-hole) |
| Lead-Free / RoHS | — | [DATA_NEEDED: lead-free status] |
| Logic Family | — | TTL-compatible I/O |