EP1810JI-45 vs EP1810JM-45 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-45 sa pamamagitan ng Altera at EP1810JM-45 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP1810JI-45 EP1810JM-45
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Manufacturer Altera (now Intel FPGA) —
Series Classic EPLD Family —
Device Type UV-Erasable / OTP Complex PLD —
Macrocell Count 48 —
Maximum Operating Frequency 33.3 MHz —
Propagation Delay (tPD) 50 ns —
Configurable I/O Lines 48 —
Dedicated Inputs 12 —
Technology CMOS EPROM CMOS, UV-EPROM configuration
Package Code QCCJ JM (windowed ceramic, UV-erasable)
Package Type 68-pin JLCC (J-leaded ceramic chip carrier) JLCC-68 (ceramic J-leaded chip carrier)
Terminal Form J BEND —
Package Shape SQUARE —
Number of Terminals 68 —
Temperature Grade INDUSTRIAL —
Temperature na Operasyon -40 °C to +85 °C -55 C to +125 C (military grade)
Volte ng Pagbibigay 5 V (TTL compatible) —
Programming Method UV-erase (windowed) / OTP via JEDEC —
Device Family — Classic EPLD (EP1810 series)
Macrocells — 48
Usable Gates — ~900 gates
Propagation Delay (tpd) — 45 ns (max, -45 speed grade)
Supply Voltage (VCC) — 4.5 V to 5.5 V
Bilang ng Pin — 68
I/O Compatibility — CMOS / TTL
Configuration Method — JEDEC fuse map, EPROM programmer
Programming Technology — UV-erasable EPROM (non-volatile, instant-on)
Uri ng Pagpapasok — Surface Mount (J-lead)
Logic Type — EPLD / PLD (programmable logic device)
Tindminan RoHS — [DATA_NEEDED: RoHS status - legacy mil-spec part]
Level ng MSL — [DATA_NEEDED: MSL level]

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