EP1810JI-45 vs EP1810JM-45 比較
詳細並排比較 EP1810JI-45 由 Altera 與 EP1810JM-45 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JI-45 | EP1810JM-45 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Manufacturer | Altera (now Intel FPGA) | — |
| Series | Classic EPLD Family | — |
| Device Type | UV-Erasable / OTP Complex PLD | — |
| Macrocell Count | 48 | — |
| Maximum Operating Frequency | 33.3 MHz | — |
| Propagation Delay (tPD) | 50 ns | — |
| Configurable I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| Technology | CMOS EPROM | CMOS, UV-EPROM configuration |
| Package Code | QCCJ | JM (windowed ceramic, UV-erasable) |
| Package Type | 68-pin JLCC (J-leaded ceramic chip carrier) | JLCC-68 (ceramic J-leaded chip carrier) |
| Terminal Form | J BEND | — |
| Package Shape | SQUARE | — |
| Number of Terminals | 68 | — |
| Temperature Grade | INDUSTRIAL | — |
| 工作溫度 | -40 °C to +85 °C | -55 C to +125 C (military grade) |
| 供應電壓 | 5 V (TTL compatible) | — |
| Programming Method | UV-erase (windowed) / OTP via JEDEC | — |
| Device Family | — | Classic EPLD (EP1810 series) |
| Macrocells | — | 48 |
| Usable Gates | — | ~900 gates |
| Propagation Delay (tpd) | — | 45 ns (max, -45 speed grade) |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V |
| 腳位數 | — | 68 |
| I/O Compatibility | — | CMOS / TTL |
| Configuration Method | — | JEDEC fuse map, EPROM programmer |
| Programming Technology | — | UV-erasable EPROM (non-volatile, instant-on) |
| 安裝類型 | — | Surface Mount (J-lead) |
| Logic Type | — | EPLD / PLD (programmable logic device) |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status - legacy mil-spec part] |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |