EP1810JI-45 vs EP1810LI-45 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810JI-45 sa pamamagitan ng Altera at EP1810LI-45 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP1810LI-45 - Classic EPLD, 900 Gates, 48 Macrocells, 45ns, PQCC68 | Rochester Electronics (Altera)
EP1810LI-45 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP1810JI-45 | EP1810LI-45 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Manufacturer | Altera (now Intel FPGA) | Rochester Electronics (licensed continuation of Altera / Intel PSG Classic EPLD line) |
| Series | Classic EPLD Family | — |
| Device Type | UV-Erasable / OTP Complex PLD | — |
| Macrocell Count | 48 | — |
| Maximum Operating Frequency | 33.3 MHz | — |
| Propagation Delay (tPD) | 50 ns | — |
| Configurable I/O Lines | 48 | — |
| Dedicated Inputs | 12 | — |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM configuration |
| Package Code | QCCJ | — |
| Package Type | 68-pin JLCC (J-leaded ceramic chip carrier) | — |
| Terminal Form | J BEND | — |
| Package Shape | SQUARE | — |
| Number of Terminals | 68 | — |
| Temperature Grade | INDUSTRIAL | — |
| Temperature na Operasyon | -40 °C to +85 °C | — |
| Volte ng Pagbibigay | 5 V (TTL compatible) | 5 V |
| Programming Method | UV-erase (windowed) / OTP via JEDEC | Altera programming hardware with MAX+PLUS II / legacy tools |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Altera Classic |
| Usable Gates | — | 900 |
| Macrocells | — | 48 |
| Maximum User I/O | — | 64 inputs / 48 outputs |
| Pin-to-Pin Logic Delay (tPD) | — | 45 ns |
| Counter Frequency (fCNT) | — | up to 100 MHz |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Hanay ng Temperature na Operasyon | — | -40 C to +85 C (Industrial, 'I' suffix) |
| Packhaging | — | 68-pin PLCC / PQCC68 (J-Lead) |
| Logic Blocks | — | 12 LABs of 4 macrocells each |
| Configuration Memory | — | Non-volatile UV-erasable EPROM |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |