EP1810LC-20 vs EP1810LC-20T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-20 sa pamamagitan ng Intel at EP1810LC-20T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1810LC-20 | EP1810LC-20T |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 900 | 900 gates |
| Macrocells | 48 | 48 |
| Maximum Operating Frequency | 50 MHz | — |
| Propagation Delay (tPD) | 20 ns | — |
| Volte ng Pagbibigay | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS EPROM | — |
| Programmability | UV-Erasable / OTP | — |
| Dedicated Inputs | 12 | — |
| Packhaging | 68-pin PLCC | — |
| Package Suffix | LC (PLCC, windowed for UV erase on L variant) | — |
| Speed Grade | 20 ns (commercial) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (socket-compatible) |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | Non-compliant (legacy 5V PLCC) |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 x 12 macrocells |
| Maximum Toggle Frequency | — | 50 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5 V |
| Package Type | — | PLCC-68 (J-lead) |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE 1149.1) and Altera Master/Slave serial |
| Shipping Format | — | Tape & Reel ("T" suffix) |