EP1810LC-20 vs EP1810LC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP1810LC-20 sa pamamagitan ng Intel at EP1810LC-35 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Rochester Electronics
EP1810LC-35 EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera

EP1810LC-35 ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EP1810LC-20 EP1810LC-35
Brand Intel Rochester Electronics
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family Classic EPLD —
Device Type EPLD (Erasable Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Usable Gates 900 —
Macrocells 48 48
Maximum Operating Frequency 50 MHz 28.6 MHz
Propagation Delay (tPD) 20 ns —
Volte ng Pagbibigay 5 V (4.75 V to 5.25 V) —
Technology CMOS EPROM CMOS, UV-erasable EPROM
Programmability UV-Erasable / OTP —
Dedicated Inputs 12 —
Packhaging 68-pin PLCC 68-pin PLCC (J-Lead)
Package Suffix LC (PLCC, windowed for UV erase on L variant) —
Speed Grade 20 ns (commercial) —
Temperature na Operasyon 0C to +70C (commercial) 0C to +70C (commercial)
Uri ng Pagpapasok Surface Mount Surface Mount (socketable)
Tindminan RoHS [DATA_NEEDED: rohs status] [DATA_NEEDED]
Series — Classic EP1810
Equivalent Gates — 900 usable / 2100 equivalent
Propagation Delay (tpd) — 35 ns (max, '-35' speed grade)
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
I/O Pins — [DATA_NEEDED: I/O count exact]
Configuration Method — UV-erase + EPROM programmer
Programmable Interconnect — Centralized Programmable Interconnect Array (PIA)
Development Tool (legacy) — MAX+PLUS II / A+PLUS
Lead-Free — [DATA_NEEDED]

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